EPC16UC88 vs EPC16UC80 Comparison
Detailed side-by-side comparison of EPC16UC88 by Altera and EPC16UC80 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPC16UC88 | EPC16UC80 |
|---|---|---|
| Brand | Altera | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Unknown | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $11.75 |
| Device Type | In-system programmable configuration PROM for FPGAs | β |
| Configuration Memory Capacity | 16 Mb | β |
| Supply Voltage | 3.3 V core and I/O | β |
| Package | 88-UBGA (11x8) | 80-ball UBGA (Ultra FineLine BGA), 11x8 mm |
| Package Family | UBGA | β |
| In-System Programmability | IEEE Std. 1532 compatible | Yes (IEEE 1149.1 JTAG) |
| Programming Language Support | Jam Standard Test and Programming Language (STAPL) | β |
| JTAG Boundary Scan | Supported | β |
| nINIT_CONF Function | Allows private JTAG instruction to start FPGA configuration | β |
| Configuration Architecture | Configuration controller and flash memory | β |
| FPGA Configuration Use | Automatic configuration after power-up or system initialization | β |
| Data Output | Configuration data output controlled by OE and nCS | β |
| Output Control | OE and nCS control tri-state buffer and address counter | β |
| Mounting Type | Surface mount | Surface Mount |
| Package Dimensions | 11 mm x 8 mm | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| REACH Status | [DATA_NEEDED: REACH status] | β |
| Operating Temperature | [DATA_NEEDED: operating temperature] | -40 C to +85 C (industrial) |
| Output Current | [DATA_NEEDED: output current] | β |
| Configuration Frequency | [DATA_NEEDED: configuration frequency] | β |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | β |
| Memory Density | β | 16 Mbit |
| Device Family | β | EPC4 / EPC8 / EPC16 Enhanced Configuration Device |
| Configuration Memory Sections | β | 8 (multi-boot capable) |
| Supply Voltage (VCC) | β | 3.0 V to 3.6 V (typical 3.3 V) |
| Configuration Clock (DCLK) | β | Up to 33 MHz (FPP mode) |
| Configuration Modes | β | FPP, PS, JTAG |
| Interface | β | Parallel data + DCLK + nSTATUS + nCONFIG + CONFIG_DONE |
| Endurance | β | 100,000 erase/program cycles (per datasheet) |
| Supported Target FPGAs | β | Stratix/II/III/GX, Cyclone/II/III, APEX 20K/II/IIE, Mercury |
| Lead-Free / RoHS | β | Compliant per Altera product page |
| Multi-Device Daisy-Chain | β | Yes |