EPC1L120 vs EPC1LC120 Comparison
Detailed side-by-side comparison of EPC1L120 by Intel and EPC1LC120 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPC1L120 - Altera/Intel Configuration Device 120 kbit Serial | PLCC-20
EPC1L120 ⚠ Last Time Buy
Specification Comparison
| Parameter | EPC1L120 | EPC1LC120 |
|---|---|---|
| Brand | Intel | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Last Time Buy | Active |
| Memory Type | Configuration EEPROM | Serial Configuration Memory (Flash-based, non-volatile) |
| Memory Capacity | 120 kbit | — |
| Interface Type | Serial (Altera configuration protocol) | — |
| Operating Supply Voltage | 3.3 V / 5 V | — |
| Output Compatibility | MultiVolt: 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V | — |
| Programmability | In-System via JTAG (IEEE 1149.1) | — |
| JTAG Support | Yes (dedicated JTAG port) | — |
| Package | PLCC-20 | LQFP-120 (Low-profile Quad Flat Pack) |
| Mounting Type | Surface Mount / Through-Hole (socket) | Surface Mount |
| Reprogram Cycles | 100 cycles typical | — |
| Operating Temperature | -40C to +85C (industrial) | — |
| Compatible Altera FPGAs | FLEX 6000, FLEX 8000, MAX 7000, MAX 9000 families | — |
| Cascade Support | Yes (multi-FPGA configuration chains) | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| MSL Level | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL rating] |
| Memory Density | — | 1 Mbit |
| Serial Clock Frequency (DCLK) | — | 8 MHz |
| Supported FPGA Families | — | APEX 20K, ACEX 1K, Cyclone, MAX, Mercury, Stratix-class |
| Interface | — | Altera / Intel proprietary FPGA-configuration serial bus (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) |
| Operating Temperature Range | — | [DATA_NEEDED: operating temperature range] |
| Supply Voltage | — | [DATA_NEEDED: VCC range] |
| Programming | — | Factory / JTAG via Altera programming tools |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Configuration Mode | — | Serial configuration of SRAM-based FPGAs |
| Compatible Bitstream Width | — | Serial |