EPC1LC120 vs EPC2LC20 Comparison

Detailed side-by-side comparison of EPC1LC120 by Altera and EPC2LC20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPC1LC120 EPC2LC20
Brand Altera Altera
Category Memory ICs Memory ICs
Lifecycle Status Active Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $9.30 $7.20
Memory Type Serial Configuration Memory (Flash-based, non-volatile) Non-volatile configuration PROM
Memory Density 1 Mbit β€”
Serial Clock Frequency (DCLK) 8 MHz β€”
Supported FPGA Families APEX 20K, ACEX 1K, Cyclone, MAX, Mercury, Stratix-class ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000
Interface Altera / Intel proprietary FPGA-configuration serial bus (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) β€”
Package LQFP-120 (Low-profile Quad Flat Pack) 20-pin PLCC (J-lead, 9x9 mm)
Mounting Type Surface Mount Surface Mount
Operating Temperature Range [DATA_NEEDED: operating temperature range] β€”
Supply Voltage [DATA_NEEDED: VCC range] β€”
Programming Factory / JTAG via Altera programming tools β€”
RoHS Status [DATA_NEEDED: RoHS compliance status] Non-Compliant (original Altera Pb-containing part)
MSL Level [DATA_NEEDED: MSL rating] β€”
Lead-Free [DATA_NEEDED: lead-free status] β€”
Configuration Mode Serial configuration of SRAM-based FPGAs β€”
Compatible Bitstream Width Serial β€”
Memory Size β€” 1.6 Mbit
Configuration Interface β€” Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE
Programming Interface β€” IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant
Supply Voltage VCC β€” 3.0 V to 3.6 V (3.3-V operation)
ISP Voltage Range β€” 5.0 V or 3.3 V
Cascade Support β€” Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams
Operating Temperature β€” -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet]
Lead-Free Version β€” EPC2LC20N available as lead-free equivalent
Programming Support β€” Altera Programming Unit (APU), Quartus II, JTAG programmer
Boundary-Scan β€” IEEE 1149.1 compliant, 8-bit or 16-bit JTAG

Datasheets & Resources

Browse All Products Create BOM Request Quote