EPC1LC120 vs EPC2LC20 Comparaison
Comparaison détaillée côte à côte de EPC1LC120 par Altera et EPC2LC20 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC1LC120 | EPC2LC20 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Actif | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,30 | $7,20 |
| Type de mémoire | Serial Configuration Memory (Flash-based, non-volatile) | Non-volatile configuration PROM |
| Memory Density | 1 Mbit | — |
| Serial Clock Frequency (DCLK) | 8 MHz | — |
| Supported FPGA Families | APEX 20K, ACEX 1K, Cyclone, MAX, Mercury, Stratix-class | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| Interface | Altera / Intel proprietary FPGA-configuration serial bus (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) | — |
| Boîtier | LQFP-120 (Low-profile Quad Flat Pack) | 20-pin PLCC (J-lead, 9x9 mm) |
| Type de montage | Surface Mount | Surface Mount |
| Plage de température de fonctionnement | [DATA_NEEDED: operating temperature range] | — |
| Tension d'alimentation | [DATA_NEEDED: VCC range] | — |
| Programming | Factory / JTAG via Altera programming tools | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | Non-Compliant (original Altera Pb-containing part) |
| Niveau MSL | [DATA_NEEDED: MSL rating] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Configuration Mode | Serial configuration of SRAM-based FPGAs | — |
| Compatible Bitstream Width | Serial | — |
| Taille de mémoire | — | 1.6 Mbit |
| Configuration Interface | — | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| Programming Interface | — | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| Supply Voltage VCC | — | 3.0 V to 3.6 V (3.3-V operation) |
| ISP Voltage Range | — | 5.0 V or 3.3 V |
| Cascade Support | — | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| Température de fonctionnement | — | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] |
| Lead-Free Version | — | EPC2LC20N available as lead-free equivalent |
| Programming Support | — | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | — | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |