EPC1LC20-W vs EPC2LC20 Comparison

Detailed side-by-side comparison of EPC1LC20-W by Altera and EPC2LC20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPC1LC20-W EPC2LC20
Brand Altera Altera
Category Memory ICs Memory ICs
Lifecycle Status Obsolete NRND
Unit Price (USD) — $7.20
Memory Type OTP (One-Time Programmable) Configuration PROM Non-volatile configuration PROM
Memory Size 1 Mbit 1.6 Mbit
Configuration Clock (DCLK) 8 MHz maximum —
Supply Voltage 3.3 V and 5.0 V —
Interface Altera serial configuration (DCLK / DATA / nCONFIG / nSTATUS) —
In-System Programming Yes - IEEE 1149.1 (JTAG) ISP at 3.3 V / 5.0 V —
Package 20-PLCC J-lead (9x9 mm) 20-pin PLCC (J-lead, 9x9 mm)
Lead Finish Pb-free (matte tin) - "-W" suffix —
Daisy-Chain Support Yes - multiple EPC1 / EPC2 devices cascade to program larger FPGAs —
Compression Support Yes - stores compressed Altera FPGA bitstreams —
Operating Temperature Range [DATA_NEEDED: operating temperature range] —
Programming Cycles 1 (OTP) —
Target FPGA Families Cyclone, FLEX 6000 / 10K / 10KE, ACEX 1K, APEX 20K, Mercury —
RoHS Status Compliant (Pb-free -W finish) Non-Compliant (original Altera Pb-containing part)
Mounting Type Surface Mount (PLCC socket or direct solder) Surface Mount
Configuration Interface — Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE
Programming Interface — IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant
Supply Voltage VCC — 3.0 V to 3.6 V (3.3-V operation)
ISP Voltage Range — 5.0 V or 3.3 V
Supported FPGA Families — ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000
Cascade Support — Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams
Operating Temperature — -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet]
Lead-Free Version — EPC2LC20N available as lead-free equivalent
Programming Support — Altera Programming Unit (APU), Quartus II, JTAG programmer
Boundary-Scan — IEEE 1149.1 compliant, 8-bit or 16-bit JTAG

Datasheets & Resources

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