EPC1LC20 vs EPC1LC20-WCEC52 Comparison

Detailed side-by-side comparison of EPC1LC20 by Intel and EPC1LC20-WCEC52 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPC1LC20 EPC1LC20-WCEC52
Brand Intel Altera
Category Memory ICs Memory ICs
Lifecycle Status Obsolete Obsolete
Memory Type Non-volatile configuration memory (Flash/EPROM) OTP Configuration PROM (Anti-fuse)
Memory Capacity 1 Mbit (1,048,576 bits) —
Interface Type Serial configuration interface —
Maximum DCLK Frequency 8 MHz —
Supply Voltage 3.3 V or 5.0 V —
In-System Programmability Yes (IEEE 1149.1 / JTAG) Yes (IEEE 1149.1 JTAG)
Programmable Voltage 5.0 V and 3.3 V ISP —
Configuration Mode Serial, multi-device daisy-chain capable —
Package 20-pin PLCC (J-leaded, surface mount) 20-pin PLCC (J-lead, through-hole, 9x9 mm)
Pin Count 20 20
Mounting Type Surface Mount —
Operating Temperature [DATA_NEEDED: Operating temperature range] -40C to +85C (industrial)
Compatible FPGA Families ACEX 1K, APEX 20K, FLEX 10K, Cyclone, Mercury Cyclone, Stratix, APEX, ACEX, MAX series
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
JTAG Pins TCK, TMS, TDI, TDO —
Memory Size — 1 Mbit (1,048,576 bits)
Organization — 212,942 x 1 bit
Interface — Serial (Altera FPP/PS configuration protocol)
Configuration Clock (DCLK) — 8 MHz maximum
Supply Voltage (VCC) — 3.3 V
I/O Voltage Tolerance — 5.0 V (FPGA interface)
Programmability — One-Time Programmable (OTP)
Package Mounting — Through-hole (also accepts PLCC socket)
Lead-Free — [DATA_NEEDED: lead-free status]
Programming Interface — JTAG (IEEE Std 1149.1) ISP
Lifecycle Status — Obsolete (recommended replacement: EPCQ family or newer serial config devices)

Datasheets & Resources

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