EPC2L120 vs EPC2L20U-HAF480119C Comparison

Detailed side-by-side comparison of EPC2L120 by Altera and EPC2L20U-HAF480119C by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Intel
EPC2L20U-HAF480119C EPC2L20U-HAF480119C - FPGA Config Device, SRAM LUT | Intel

EPC2L20U-HAF480119C - FPGA Config Device, SRAM LUT | Intel

EPC2L20U-HAF480119C ⚠ Last Time Buy

Specification Comparison

Parameter EPC2L120 EPC2L20U-HAF480119C
Brand Altera Intel
Category Memory ICs Memory ICs
Lifecycle Status NRND Last Time Buy
Memory Type Configuration PROM (Flash-based) Configuration PROM (non-volatile)
Density 120 Kbit —
Configuration Interface Serial, FPGA-targeted —
Operating Voltage 2.7 V to 3.6 V (3.3 V typ) —
In-System Programmability Yes (IEEE 1149.1 JTAG) —
Package PLCC-20 PLCC-20
Compatible FPGAs Altera Cyclone, Cyclone II, APEX-series —
Operating Temperature -40 C to +85 C —
CONF_DONE Output Open-drain, wire-OR capable —
Data Retention 20 years (per Altera datasheet family) —
Program/Erase Cycles 100 cycles minimum —
Mounting Type Surface Mount Surface Mount / Socketed
RoHS Status unknown [DATA_NEEDED: RoHS status]
Lead-Free unknown [DATA_NEEDED: lead-free status]
Family EPC2 (Enhanced Configuration) —
Memory Size — 1.6 Mb
Target Device — SRAM-based LUT FPGAs (Cyclone, Stratix, APEX families)
Core Supply Voltage — 3.3 V
I/O Tolerance — 5 V tolerant
Configuration Modes — Serial (1-bit), Parallel (8-bit FPP), JTAG
JTAG Support — Yes (IEEE 1149.1 boundary-scan)
Programmability — In-system programmable via JTAG
Cascade Support — Yes (multi-PROM chains for larger FPGAs)
Configuration Clock Range — 10 MHz to 40 MHz
Bitstream Compression Support — Yes (Cyclone/Stratix compressed bitstreams)
Operating Temperature Range — [DATA_NEEDED: operating temperature range]

Datasheets & Resources

Browse All Products Create BOM Request Quote