EPC2L120 vs EPC2L20U-HAF480119C 比較

詳細並排比較 EPC2L120 由 Altera 與 EPC2L20U-HAF480119C 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Intel
EPC2L20U-HAF480119C EPC2L20U-HAF480119C - FPGA Config Device, SRAM LUT | Intel

EPC2L20U-HAF480119C - FPGA Config Device, SRAM LUT | Intel

EPC2L20U-HAF480119C ⚠ 最後購買機會

規格比較

參數 EPC2L120 EPC2L20U-HAF480119C
品牌 Altera Intel
類別 Memory ICs Memory ICs
生命週期狀態 NRND 最後購買
記憶體類型 Configuration PROM (Flash-based) Configuration PROM (non-volatile)
Density 120 Kbit —
Configuration Interface Serial, FPGA-targeted —
Operating Voltage 2.7 V to 3.6 V (3.3 V typ) —
In-System Programmability Yes (IEEE 1149.1 JTAG) —
封裝 PLCC-20 PLCC-20
Compatible FPGAs Altera Cyclone, Cyclone II, APEX-series —
工作溫度 -40 C to +85 C —
CONF_DONE Output Open-drain, wire-OR capable —
Data Retention 20 years (per Altera datasheet family) —
Program/Erase Cycles 100 cycles minimum —
安裝類型 Surface Mount Surface Mount / Socketed
RoHS 狀態 unknown [DATA_NEEDED: RoHS status]
Lead-Free unknown [DATA_NEEDED: lead-free status]
Family EPC2 (Enhanced Configuration) —
記憶體容量 — 1.6 Mb
Target Device — SRAM-based LUT FPGAs (Cyclone, Stratix, APEX families)
Core Supply Voltage — 3.3 V
I/O Tolerance — 5 V tolerant
Configuration Modes — Serial (1-bit), Parallel (8-bit FPP), JTAG
JTAG Support — Yes (IEEE 1149.1 boundary-scan)
Programmability — In-system programmable via JTAG
Cascade Support — Yes (multi-PROM chains for larger FPGAs)
Configuration Clock Range — 10 MHz to 40 MHz
Bitstream Compression Support — Yes (Cyclone/Stratix compressed bitstreams)
工作溫度範圍 — [DATA_NEEDED: operating temperature range]

資料表與資源

瀏覽所有產品 建立 BOM 索取報價