EPC2L20U-HAF480119C vs EPC2L120N Comparison
Detailed side-by-side comparison of EPC2L20U-HAF480119C by Intel and EPC2L120N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPC2L20U-HAF480119C - FPGA Config Device, SRAM LUT | Intel
EPC2L20U-HAF480119C β Last Time Buy
Specification Comparison
| Parameter | EPC2L20U-HAF480119C | EPC2L120N |
|---|---|---|
| Brand | Intel | Intel |
| Category | Memory ICs | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.75 | $7.85 |
| Memory Type | Configuration PROM (non-volatile) | β |
| Memory Size | 1.6 Mb | β |
| Target Device | SRAM-based LUT FPGAs (Cyclone, Stratix, APEX families) | β |
| Core Supply Voltage | 3.3 V | β |
| I/O Tolerance | 5 V tolerant | β |
| Configuration Modes | Serial (1-bit), Parallel (8-bit FPP), JTAG | β |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | β |
| Programmability | In-system programmable via JTAG | β |
| Cascade Support | Yes (multi-PROM chains for larger FPGAs) | β |
| Configuration Clock Range | 10 MHz to 40 MHz | β |
| Bitstream Compression Support | Yes (Cyclone/Stratix compressed bitstreams) | β |
| Package | PLCC-20 | 84-pin PLCC (J-Lead) |
| Mounting Type | Surface Mount / Socketed | β |
| Operating Temperature Range | [DATA_NEEDED: operating temperature range] | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| Device Type | β | Configuration Device for SRAM-based LUT FPGAs |
| Manufacturer | β | Intel (formerly Altera) |
| Family | β | EPC2 (Enhanced Configuration Device) |
| Memory Capacity | β | 165,888 bits (400,000 gates equivalent) |
| Operating Voltage (VCCIO) | β | 2.7 V to 3.6 V |
| 5V Tolerance | β | Yes (5V-tolerant I/O) |
| Configuration Clock (FPP) | β | Up to 66 MHz |
| Configuration Clock (PS) | β | Up to 33 MHz |
| Internal Oscillator | β | 8 MHz with programmable divider |
| JTAG Interface | β | IEEE Std 1149.1 compliant, ISP support |
| Programming Cycles | β | 100,000 erase/program cycles |
| Sector Erase Time | β | [DATA_NEEDED: typical sector erase time] |
| Configuration Schemes | β | FPP, PS, JTAG, daisy chain |
| Operating Temperature | β | [DATA_NEEDED: industrial temp range] |
| Supported FPGA Families | β | Cyclone, APEX, FLEX, Mercury, ACEX, Stratix |