EPC2L20U-HAF480119C vs EPC2L120N Сравнение
Подробное сравнение бок о бок EPC2L20U-HAF480119C от Intel и EPC2L120N от Intel. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Intel
EPC2L20U-HAF480119C - FPGA Config Device, SRAM LUT | Intel
EPC2L20U-HAF480119C ⚠ Последняя закупка
Сравнение характеристик
| Параметр | EPC2L20U-HAF480119C | EPC2L120N |
|---|---|---|
| Бренд | Intel | Intel |
| Категория | Memory ICs | FPGA & CPLD |
| Статус жизненного цикла | Последняя закупка | Obsolete |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $10,75 | $7,85 |
| Тип памяти | Configuration PROM (non-volatile) | — |
| Размер памяти | 1.6 Mb | — |
| Target Device | SRAM-based LUT FPGAs (Cyclone, Stratix, APEX families) | — |
| Core Supply Voltage | 3.3 V | — |
| I/O Tolerance | 5 V tolerant | — |
| Configuration Modes | Serial (1-bit), Parallel (8-bit FPP), JTAG | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | — |
| Programmability | In-system programmable via JTAG | — |
| Cascade Support | Yes (multi-PROM chains for larger FPGAs) | — |
| Configuration Clock Range | 10 MHz to 40 MHz | — |
| Bitstream Compression Support | Yes (Cyclone/Stratix compressed bitstreams) | — |
| Корпус | PLCC-20 | 84-pin PLCC (J-Lead) |
| Тип монтажа | Surface Mount / Socketed | — |
| Диапазон рабочих температур | [DATA_NEEDED: operating temperature range] | — |
| Статус RoHS | [DATA_NEEDED: RoHS status] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Type | — | Configuration Device for SRAM-based LUT FPGAs |
| Manufacturer | — | Intel (formerly Altera) |
| Family | — | EPC2 (Enhanced Configuration Device) |
| Memory Capacity | — | 165,888 bits (400,000 gates equivalent) |
| Operating Voltage (VCCIO) | — | 2.7 V to 3.6 V |
| 5V Tolerance | — | Yes (5V-tolerant I/O) |
| Configuration Clock (FPP) | — | Up to 66 MHz |
| Configuration Clock (PS) | — | Up to 33 MHz |
| Internal Oscillator | — | 8 MHz with programmable divider |
| JTAG Interface | — | IEEE Std 1149.1 compliant, ISP support |
| Programming Cycles | — | 100,000 erase/program cycles |
| Sector Erase Time | — | [DATA_NEEDED: typical sector erase time] |
| Configuration Schemes | — | FPP, PS, JTAG, daisy chain |
| Рабочая температура | — | [DATA_NEEDED: industrial temp range] |
| Supported FPGA Families | — | Cyclone, APEX, FLEX, Mercury, ACEX, Stratix |