EPC2L20U-HAF480119C vs EPC2L20N Comparison
Detailed side-by-side comparison of EPC2L20U-HAF480119C by Intel and EPC2L20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPC2L20U-HAF480119C - FPGA Config Device, SRAM LUT | Intel
EPC2L20U-HAF480119C ⚠ Last Time BuySpecification Comparison
| Parameter | EPC2L20U-HAF480119C | EPC2L20N |
|---|---|---|
| Brand | Intel | Altera |
| Category | Memory ICs | Memory ICs |
| Lifecycle Status | Last Time Buy | NRND |
| Memory Type | Configuration PROM (non-volatile) | — |
| Memory Size | 1.6 Mb | 1.6 Mbit |
| Target Device | SRAM-based LUT FPGAs (Cyclone, Stratix, APEX families) | — |
| Core Supply Voltage | 3.3 V | — |
| I/O Tolerance | 5 V tolerant | — |
| Configuration Modes | Serial (1-bit), Parallel (8-bit FPP), JTAG | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | — |
| Programmability | In-system programmable via JTAG | — |
| Cascade Support | Yes (multi-PROM chains for larger FPGAs) | Yes (multi-PROM chain via CE control) |
| Configuration Clock Range | 10 MHz to 40 MHz | — |
| Bitstream Compression Support | Yes (Cyclone/Stratix compressed bitstreams) | — |
| Package | PLCC-20 | — |
| Mounting Type | Surface Mount / Socketed | Surface Mount (J-Lead PLCC) |
| Operating Temperature Range | [DATA_NEEDED: operating temperature range] | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | Compliant |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Function | — | In-System Programmable Configuration PROM for SRAM-based LUT FPGAs |
| Programmable Type | — | In System Programmable (ISP) |
| Supply Voltage - VCCINT/VCCIO | — | 3.0 V to 3.6 V or 4.5 V to 5.5 V |
| Package / Case | — | 20-LCC (J-Lead), PLCC-20 |
| Packaging | — | Tube |
| Operating Temperature | — | 0C to +70C (commercial) |
| Supported FPGA Families | — | Altera APEX, ACEX, Cyclone, FLEX 10K, Mercury (per datasheet) |
| Configuration Interface | — | Serial (Altera FPP / PS configuration scheme) |
| Programming Method | — | In-system via 4-wire ISP / JTAG-style |
| Pin Count | — | 20 |
| Lead Finish | — | Matte Tin (Pb-free) |
| MSL Level | — | 3 (168 hours) |