EPC2L20U-HAF480119C vs EPC2L20N 比較
詳細並排比較 EPC2L20U-HAF480119C 由 Intel 與 EPC2L20N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC2L20U-HAF480119C | EPC2L20N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | Memory ICs | Memory ICs |
| 生命週期狀態 | 最後購買 | NRND |
| 記憶體類型 | Configuration PROM (non-volatile) | — |
| 記憶體容量 | 1.6 Mb | 1.6 Mbit |
| Target Device | SRAM-based LUT FPGAs (Cyclone, Stratix, APEX families) | — |
| Core Supply Voltage | 3.3 V | — |
| I/O Tolerance | 5 V tolerant | — |
| Configuration Modes | Serial (1-bit), Parallel (8-bit FPP), JTAG | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | — |
| Programmability | In-system programmable via JTAG | — |
| Cascade Support | Yes (multi-PROM chains for larger FPGAs) | Yes (multi-PROM chain via CE control) |
| Configuration Clock Range | 10 MHz to 40 MHz | — |
| Bitstream Compression Support | Yes (Cyclone/Stratix compressed bitstreams) | — |
| 封裝 | PLCC-20 | — |
| 安裝類型 | Surface Mount / Socketed | Surface Mount (J-Lead PLCC) |
| 工作溫度範圍 | [DATA_NEEDED: operating temperature range] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | Compliant |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| 功能 | — | In-System Programmable Configuration PROM for SRAM-based LUT FPGAs |
| Programmable Type | — | In System Programmable (ISP) |
| Supply Voltage - VCCINT/VCCIO | — | 3.0 V to 3.6 V or 4.5 V to 5.5 V |
| 封裝 / 外殼 | — | 20-LCC (J-Lead), PLCC-20 |
| Packaging | — | Tube |
| 工作溫度 | — | 0C to +70C (commercial) |
| Supported FPGA Families | — | Altera APEX, ACEX, Cyclone, FLEX 10K, Mercury (per datasheet) |
| Configuration Interface | — | Serial (Altera FPP / PS configuration scheme) |
| Programming Method | — | In-system via 4-wire ISP / JTAG-style |
| 腳位數 | — | 20 |
| Lead Finish | — | Matte Tin (Pb-free) |
| MSL 等級 | — | 3 (168 hours) |