EPC2LC20NU vs EPC2LC20 Comparison

Detailed side-by-side comparison of EPC2LC20NU by Altera and EPC2LC20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPC2LC20NU EPC2LC20
Brand Altera Altera
Category Memory ICs Memory ICs
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $8.20 $7.20
Function In-System Programmable Configuration PROM β€”
Memory Density 1.6 Mbit β€”
FPGA Interface Altera serial (4-pin: nCS, DCLK, DATA, nINIT_CONF) β€”
Supply Voltage (VCC) 3.0 V to 3.6 V β€”
I/O Tolerance 5 V tolerant inputs (per datasheet, except JTAG pins) β€”
Programming Method In-system via IEEE 1149.1 JTAG β€”
JTAG Support Yes (IEEE Std 1149.1 boundary-scan compliant) β€”
Cascade Support Yes - daisy-chain for larger bitstreams Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams
Minimum DC Input -0.3 V (inputs may undershoot to -2.0 V for <20 ns) β€”
Maximum Overshoot 7.0 V for <100 mA and <20 ns β€”
Package 20-pin J-lead PLCC (9x9 mm) 20-pin PLCC (J-lead, 9x9 mm)
Mounting Type Surface Mount Surface Mount
Lead-Free / RoHS Non-LEAD / non-RoHS (NU suffix = matte tin Sn finish, not Pb-free) β€”
Operating Temperature 0C to +70C (commercial) -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet]
Compatibility Altera APEX 20K, APEX II, Mercury, FLEX 10K, ACEX 1K, Cyclone (legacy serial configuration) β€”
Memory Type β€” Non-volatile configuration PROM
Memory Size β€” 1.6 Mbit
Configuration Interface β€” Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE
Programming Interface β€” IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant
Supply Voltage VCC β€” 3.0 V to 3.6 V (3.3-V operation)
ISP Voltage Range β€” 5.0 V or 3.3 V
Supported FPGA Families β€” ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000
RoHS Status β€” Non-Compliant (original Altera Pb-containing part)
Lead-Free Version β€” EPC2LC20N available as lead-free equivalent
Programming Support β€” Altera Programming Unit (APU), Quartus II, JTAG programmer
Boundary-Scan β€” IEEE 1149.1 compliant, 8-bit or 16-bit JTAG

Datasheets & Resources

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