EPC2LC20NUBAF48 vs EPC2LC20-V Comparison

Detailed side-by-side comparison of EPC2LC20NUBAF48 by Altera and EPC2LC20-V by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPC2LC20NUBAF48 EPC2LC20-V
Brand Altera Altera
Category FPGA & CPLD Memory ICs
Lifecycle Status Obsolete Obsolete
Memory Type Non-volatile flash configuration PROM Configuration PROM (Flash-based, in-system programmable)
Memory Density 2 Mbit (2,097,152 bits) 1.6 Mbit
Core Supply Voltage (VCC) 3.3 V (low-voltage 'L' variant) —
I/O Logic Levels 3.3 V LVCMOS (5V-tolerant inputs) —
Configuration Interface Altera serial (DATA, DCLK, nCS, ASDO) Serial (Altera FPP/PS modes via DCLK/nSTATUS/CONF_DONE)
JTAG / ISP Support IEEE 1532 / JTAG in-system programming —
Cascade Support Yes - dedicated nCASC pin for 2-device chains Yes, daisy-chainable for >1.6 Mbit designs
Programming Voltage Internal 3.3V generation, no external VPP —
FPGA Compatibility APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, FLEX 6000 —
Package 20-pin Ultra FineLine BGA (UBGA, NU suffix) —
Operating Temperature -40C to +85C (industrial) —
Configuration Clock Internal oscillator (DCLK output to FPGA) —
Programming Tools Quartus II Programmer, ByteBlaster II, USB-Blaster —
RoHS Status [DATA_NEEDED: RoHS status] Compliant (per distributor listings)
Lead-Free [DATA_NEEDED: lead-free status] Yes
Maximum Configuration Clock — 10 MHz
Supply Voltage VCC — 3.3 V
I/O Tolerance — 5 V tolerant on configuration pins
In-System Programming — Yes, via IEEE 1149.1 JTAG (TMS/TCK/TDI/TDO)
Operating Temperature Range (V suffix) — 0 °C to +70 °C (commercial)
Package Type — 20-pin PLCC (JEDEC MS-018)
Package Dimensions — 9 x 9 mm body, 1.27 mm pitch
Mounting Type — Surface Mount (PLCC socket compatible)
Supported FPGA Families — APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, MAX 9000

Datasheets & Resources

Browse All Products Create BOM Request Quote