EPC2LC20NUBAF48 vs EPC2LC20-V 비교

다음의 상세 나란히 비교: EPC2LC20NUBAF48 제조: Altera 및 EPC2LC20-V 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPC2LC20NUBAF48 EPC2LC20-V
브랜드 Altera Altera
카테고리 FPGA & CPLD Memory ICs
수명 주기 상태 Obsolete Obsolete
재고 상태 In Stock In Stock
단가 (USD) $16.40 $9.45
메모리 유형 Non-volatile flash configuration PROM Configuration PROM (Flash-based, in-system programmable)
Memory Density 2 Mbit (2,097,152 bits) 1.6 Mbit
Core Supply Voltage (VCC) 3.3 V (low-voltage 'L' variant) —
I/O Logic Levels 3.3 V LVCMOS (5V-tolerant inputs) —
Configuration Interface Altera serial (DATA, DCLK, nCS, ASDO) Serial (Altera FPP/PS modes via DCLK/nSTATUS/CONF_DONE)
JTAG / ISP Support IEEE 1532 / JTAG in-system programming —
Cascade Support Yes - dedicated nCASC pin for 2-device chains Yes, daisy-chainable for >1.6 Mbit designs
Programming Voltage Internal 3.3V generation, no external VPP —
FPGA Compatibility APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, FLEX 6000 —
패키지 20-pin Ultra FineLine BGA (UBGA, NU suffix) —
동작 온도 -40C to +85C (industrial) —
Configuration Clock Internal oscillator (DCLK output to FPGA) —
Programming Tools Quartus II Programmer, ByteBlaster II, USB-Blaster —
RoHS 상태 [DATA_NEEDED: RoHS status] Compliant (per distributor listings)
Lead-Free [DATA_NEEDED: lead-free status] Yes
Maximum Configuration Clock — 10 MHz
Supply Voltage VCC — 3.3 V
I/O Tolerance — 5 V tolerant on configuration pins
In-System Programming — Yes, via IEEE 1149.1 JTAG (TMS/TCK/TDI/TDO)
Operating Temperature Range (V suffix) — 0 °C to +70 °C (commercial)
Package Type — 20-pin PLCC (JEDEC MS-018)
Package Dimensions — 9 x 9 mm body, 1.27 mm pitch
실장 유형 — Surface Mount (PLCC socket compatible)
Supported FPGA Families — APEX 20K, ACEX 1K, FLEX 10K, FLEX 6000, MAX 9000

데이터시트 & 자료

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