EPC2T132U vs EPC2TC32N Comparison

Detailed side-by-side comparison of EPC2T132U by Intel and EPC2TC32N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPC2T132U EPC2TC32N
Brand Intel Altera
Category Memory ICs Memory ICs
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $0.00 $9.20
Manufacturer Intel (formerly Altera) Altera (now Intel)
Product Type FPGA Configuration Device (Boot PROM) β€”
Target FPGAs Altera APEX II, Cyclone, Stratix, and other SRAM-based LUT FPGAs β€”
Configuration Memory Size [DATA_NEEDED: configuration memory size in bits] β€”
Supply Voltage 3.3 V β€”
Interface Serial (Passive Serial), JTAG (IEEE 1149.1), Passive Parallel JTAG (IEEE 1149.1) + serial/parallel
In-System Programmability Yes (via JTAG) β€”
JTAG Support Yes (IEEE 1149.1 compliant TAP) β€”
Configuration Clock Internal oscillator (no external crystal required) β€”
Data Compression Yes (up to 2x compression vs competing PROMs) β€”
Operating Temperature [DATA_NEEDED: operating temperature range] 0 Β°C to +70 Β°C (Commercial)
Package 132-pin UQFP (Ultra-thin Quad Flat Pack) 32-TQFP (7x7 mm)
Mounting Type Surface Mount Surface Mount
MSL Level [DATA_NEEDED: MSL level] β€”
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Lead-Free [DATA_NEEDED: lead-free status] β€”
Lifecycle Status Obsolete (per Altera/Intel product discontinuance) β€”
Compatible Quartus Version [DATA_NEEDED: Quartus version supporting EPC2] β€”
Memory Type β€” Flash Configuration PROM
Memory Size β€” 1.6 Mbit
Programmable Type β€” In System Programmable (ISP)
Supply Voltage - VCCINT β€” 3.0 V to 3.6 V or 4.75 V to 5.25 V
Supply Voltage - VCCIO β€” 3.0 V to 3.6 V or 4.75 V to 5.25 V
Max Configuration Clock β€” 8 MHz
Supported FPGA Families β€” ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX
Daisy-Chain Support β€” Yes (multi-FPGA cascade)
JTAG Compliance β€” IEEE 1149.1
Configuration Mode β€” Serial (AS) or Parallel (PS/AP)

Datasheets & Resources

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