EPF10K200SFC672-2 vs EPF10K130EFC672-2 Comparison
Detailed side-by-side comparison of EPF10K200SFC672-2 by Altera and EPF10K130EFC672-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPF10K200SFC672-2 | EPF10K130EFC672-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $320.00 | $61.75 |
| Series | FLEX 10KE | β |
| Logic Elements | 9,984 | β |
| System Gates | 200,000 | β |
| Logic Array Blocks (LABs) | 1,248 | 832 |
| User I/O Pins | 470 | β |
| Embedded Memory (bits) | 98,304 | β |
| Process Technology | 0.22 Β΅m CMOS | 0.22 Β΅m CMOS |
| Core Supply Voltage | 2.5 V (2.375 V to 2.625 V) | 2.5 V |
| I/O Supply Voltage | MultiVolt 2.5 V / 3.3 V / 5.0 V | β |
| Speed Grade | -2 | -2 |
| Internal Propagation Delay | 0.4 ns | β |
| Maximum Operating Frequency | 200 MHz | β |
| Package | 672-pin FineLine BGA (FBGA), 45 Γ 45 mm, 1.27 mm pitch | 672-ball FineLine BGA |
| Operating Temperature | 0 Β°C to +70 Β°C (Commercial) | 0 Β°C to +70 Β°C (Commercial) |
| Configuration Method | SRAM-based, passive parallel asynchronous | β |
| Boundary Scan | IEEE 1149.1 (JTAG) | β |
| On-chip PLL | Yes | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | β |
| Family | β | FLEX 10KE |
| Logic Elements / Cells | β | 6,656 |
| Total Gates | β | ~130,000 |
| Embedded Memory (RAM bits) | β | 65,536 |
| Maximum User I/Os | β | 413 |
| Number of I/O Pins | β | 672 (package pins) |
| Propagation Delay (typ.) | β | 0.6 ns |
| Internal Operating Frequency (max) | β | 333.33 MHz |
| Programming Method | β | SRAM-based, JTAG (IEEE 1149.1) |
| Mounting Type | β | Surface Mount (BGA) |