EPF10K200SFC672-2 vs EPF10K130EFC672-2 比較
詳細並排比較 EPF10K200SFC672-2 由 Altera 與 EPF10K130EFC672-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPF10K200SFC672-2 | EPF10K130EFC672-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Series | FLEX 10KE | — |
| Logic Elements | 9,984 | — |
| System Gates | 200,000 | — |
| Logic Array Blocks (LABs) | 1,248 | 832 |
| User I/O Pins | 470 | — |
| Embedded Memory (bits) | 98,304 | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Core Supply Voltage | 2.5 V (2.375 V to 2.625 V) | 2.5 V |
| I/O Supply Voltage | MultiVolt 2.5 V / 3.3 V / 5.0 V | — |
| Speed Grade | -2 | -2 |
| Internal Propagation Delay | 0.4 ns | — |
| Maximum Operating Frequency | 200 MHz | — |
| 封裝 | 672-pin FineLine BGA (FBGA), 45 × 45 mm, 1.27 mm pitch | 672-ball FineLine BGA |
| 工作溫度 | 0 °C to +70 °C (Commercial) | 0 °C to +70 °C (Commercial) |
| Configuration Method | SRAM-based, passive parallel asynchronous | — |
| Boundary Scan | IEEE 1149.1 (JTAG) | — |
| On-chip PLL | Yes | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | — |
| Family | — | FLEX 10KE |
| Logic Elements / Cells | — | 6,656 |
| Total Gates | — | ~130,000 |
| Embedded Memory (RAM bits) | — | 65,536 |
| Maximum User I/Os | — | 413 |
| Number of I/O Pins | — | 672 (package pins) |
| Propagation Delay (typ.) | — | 0.6 ns |
| Internal Operating Frequency (max) | — | 333.33 MHz |
| Programming Method | — | SRAM-based, JTAG (IEEE 1149.1) |
| 安裝類型 | — | Surface Mount (BGA) |