EPF8820ARC208-2 vs EPF8820ARC208-2A Comparison
Detailed side-by-side comparison of EPF8820ARC208-2 by Altera and EPF8820ARC208-2A by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPF8820ARC208-2A - FLEX 8000 FPGA, 672 Logic Elements, 152 I/O | Altera
EPF8820ARC208-2A ObsoleteSpecification Comparison
| Parameter | EPF8820ARC208-2 | EPF8820ARC208-2A |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.95 | $14.10 |
| Family | FLEX 8000 | FLEX 8000 |
| Logic Cells | 672 | β |
| Usable Gates | 8,000 (typical) | β |
| Registers | 1,500 (max) | β |
| User I/O Pins | 152 | 152 |
| Package | 208-pin RQFP / BFQFP with exposed pad | 208-pin S-PQFP (Shrink Plastic Quad Flat Pack) with exposed pad |
| Process Technology | 0.42 Β΅m CMOS | CMOS SRAM |
| Supply Voltage (Core) | 5 V | β |
| I/O Voltage (MultiVolt) | 3.3 V or 5.0 V | β |
| Speed Grade | -2 | β |
| Max Internal Frequency | 125 MHz | β |
| Configuration Method | SRAM - serial EPC device, parallel EPROM, or microcontroller | Serial SRAM, EPC1/EPC1064/EPC1213/EPC1441 PROM, or controller |
| In-Circuit Reconfigurable | Yes (ICR) | β |
| Boundary-Scan / JTAG | Yes | β |
| Operating Temperature | Commercial (0 Β°C to +70 Β°C) | 0 Β°C to 70 Β°C (commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: check distributor listing] |
| Device Type | β | FPGA (Field Programmable Gate Array) |
| Logic Elements | β | 672 |
| Logic Array Blocks (LABs) | β | 84 |
| Embedded Array Blocks (EABs) | β | [DATA_NEEDED: EAB count] |
| Dedicated Inputs | β | 4 |
| Total RAM Bits | β | [DATA_NEEDED: distributed RAM bits] |
| Supply Voltage (VCCINT) | β | 4.75 V to 5.25 V |
| I/O Supply Voltage (VCCIO) | β | 3.3 V or 5.0 V selectable |
| Propagation Delay (tPD) | β | 5 ns (typical, -2A speed grade) |
| Terminal Pitch | β | 0.500 mm |
| JTAG Support | β | Yes (IEEE 1149.1 boundary-scan) |