EPF8820ARC208-2 vs EPF8820ARC208-2A Vergleich
Detaillierter Direktvergleich von EPF8820ARC208-2 von Altera und EPF8820ARC208-2A von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPF8820ARC208-2A - FLEX 8000 FPGA, 672 Logic Elements, 152 I/O | Altera
EPF8820ARC208-2A ObsoleteSpezifikationsvergleich
| Parameter | EPF8820ARC208-2 | EPF8820ARC208-2A |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,95 | $14,10 |
| Family | FLEX 8000 | FLEX 8000 |
| Logic Cells | 672 | — |
| Usable Gates | 8,000 (typical) | — |
| Registers | 1,500 (max) | — |
| User I/O Pins | 152 | 152 |
| Gehäuse | 208-pin RQFP / BFQFP with exposed pad | 208-pin S-PQFP (Shrink Plastic Quad Flat Pack) with exposed pad |
| Process Technology | 0.42 µm CMOS | CMOS SRAM |
| Supply Voltage (Core) | 5 V | — |
| I/O Voltage (MultiVolt) | 3.3 V or 5.0 V | — |
| Speed Grade | -2 | — |
| Max Internal Frequency | 125 MHz | — |
| Configuration Method | SRAM - serial EPC device, parallel EPROM, or microcontroller | Serial SRAM, EPC1/EPC1064/EPC1213/EPC1441 PROM, or controller |
| In-Circuit Reconfigurable | Yes (ICR) | — |
| Boundary-Scan / JTAG | Yes | — |
| Betriebstemperatur | Commercial (0 °C to +70 °C) | 0 °C to 70 °C (commercial) |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: check distributor listing] |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Logic Elements | — | 672 |
| Logic Array Blocks (LABs) | — | 84 |
| Embedded Array Blocks (EABs) | — | [DATA_NEEDED: EAB count] |
| Dedicated Inputs | — | 4 |
| Total RAM Bits | — | [DATA_NEEDED: distributed RAM bits] |
| Supply Voltage (VCCINT) | — | 4.75 V to 5.25 V |
| I/O Supply Voltage (VCCIO) | — | 3.3 V or 5.0 V selectable |
| Propagation Delay (tPD) | — | 5 ns (typical, -2A speed grade) |
| Terminal Pitch | — | 0.500 mm |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |