EPM240GT100C3N vs EPM240T100C5N Comparison

Detailed side-by-side comparison of EPM240GT100C3N by Intel and EPM240T100C5N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM240GT100C3N EPM240T100C5N
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Active
Manufacturer Intel (formerly Altera) —
Series MAX II —
Device Family MAX II G (instant-on, non-volatile CPLD) —
Logic Elements (LE) 240 —
Equivalent Macrocells 192 192
User I/O Pins 80 —
User Flash Memory (UFM) 8 Kbits —
Pin-to-Pin Delay (tPD) 4.7 ns —
Process Technology 0.18 µm 6-layer-metal flash 0.18 µm, 6-layer-metal flash
Core Voltage 3.3 V —
MultiVolt I/O Standards LVTTL, LVCMOS, PCI, SSTL (1.5 V / 1.8 V / 2.5 V / 3.3 V) —
Programmability In-System Programmable (ISP) via JTAG —
Package TQFP-100 (GT100), 16 x 16 mm, 0.5 mm pitch 100-pin TQFP (T100), 14x14 mm
Operating Temperature 0 °C to +85 °C (commercial, suffix C) 0 °C to +85 °C (commercial, 'C' suffix)
Lead-Free / RoHS Lead Free, RoHS Compliant —
Mounting Type Surface Mount Surface Mount
Family — MAX II
Device Type — CPLD (Complex Programmable Logic Device)
Logic Elements (LEs) — 240
On-Chip User Flash — 8 Kbits
Maximum User I/O Pins — 80
Number of I/O Banks — 4
Pin-to-Pin Delay (speed grade 5) — 4.7 ns
Maximum Internal Frequency — 201.1 MHz
Core Supply Voltage (VCCINT) — 2.5 V / 3.3 V
I/O Supply Voltage (VCCIO) — 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt)
Programming Interface — JTAG (IEEE 1149.1) / ISP
RoHS Status — Compliant (lead-free)

Datasheets & Resources

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