EPM240GT100I5N vs EPM240GF100I5N Comparison

Detailed side-by-side comparison of EPM240GT100I5N by Altera and EPM240GF100I5N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM240GT100I5N EPM240GF100I5N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Active
Product Type CPLD (Complex Programmable Logic Device) —
Family MAX II —
Logic Elements (LEs) 240 —
Equivalent Macrocells 192 —
User I/Os 80 —
Propagation Delay (tPD) 4.7 ns —
Internal Performance (fMAX) 304 MHz —
Embedded Non-Volatile Memory 8 Kbits user Flash —
Process Technology 0.18 µm 6-layer-metal Flash CMOS —
Supply Voltage - Core (VCCINT) 1.71 V to 1.89 V (3.3 V tolerant for MAX II G variant) —
I/O Bank Voltage (VCCIO) 1.5 V / 1.8 V / 2.5 V / 3.3 V MultiVolt I/O —
Programming Interface JTAG (IEEE 1149.1) ISP —
Package 100-pin TQFP (14x14 mm, 0.5 mm pitch) 100-ball FBGA (FineLine BGA), 11 mm x 11 mm, 1.0 mm pitch
Operating Temperature -40 °C to +100 °C (Industrial) —
Lead-Free / RoHS Yes (suffix N) Yes (lead-free, RoHS compliant)
Mounting Type Surface Mount Surface Mount
Series — MAX II
Logic Elements / Blocks — 240 LE
Number of Macrocells — 192
Maximum User I/O — 80
Propagation Delay (tpd, max) — 4.7 ns
Programmable Type — In-System Programmable (ISP)
Non-Volatile Memory — On-chip flash configuration
Internal Supply Voltage — 1.71 V to 1.89 V (regulated on-chip)
I/O Supply Voltage (VCCIO) — 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt)
Operating Temperature (TJ) — -40 C to +100 C
JTAG Support — IEEE 1149.1 / IEEE 1532 compliant
Logic Family — CMOS
Vertical Migration Family — EPM240 / EPM570 / EPM1270 / EPM2210 in same-package footprint

Datasheets & Resources

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