EPM3032ATC44-10NAB vs EPM3032ATC44-4 Comparison
Detailed side-by-side comparison of EPM3032ATC44-10NAB by Intel and EPM3032ATC44-4 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM3032ATC44-10NAB - 32-Macrocell CPLD, 10ns, 3.3V | Intel (Altera)
EPM3032ATC44-10NAB ObsoleteIntel
EPM3032ATC44-4 - MAX 3000A CPLD, 32 Macrocells, 44-TQFP | Intel
EPM3032ATC44-4 β Last Time BuySpecification Comparison
| Parameter | EPM3032ATC44-10NAB | EPM3032ATC44-4 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $4.10 | $1.74 |
| Product Family | MAX 3000A | β |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Logic Elements / Macrocells | 32 macrocells | β |
| Usable Gates | 600 | β |
| Pin-to-Pin Delay (tPD) | 10 ns | β |
| Maximum Operating Frequency | 103.1 MHz (per Arrow listing) | β |
| Number of User I/O | 34 (max for 44-pin TQFP package) | β |
| Core Supply Voltage (VCCINT) | 3.3 V | β |
| I/O Supply Voltage (VCCIO) | 3.3 V (MultiVolt I/O compatible with 5.0 V, 3.3 V, 2.5 V logic) | β |
| Package | 44-pin TQFP | 44-pin TQFP |
| Mounting Type | Surface Mount | β |
| Programming Interface | JTAG (IEEE Std. 1149.1 / IEEE Std. 1532 ISP) | β |
| Configuration Memory | Non-volatile EEPROM | Non-volatile EEPROM |
| Hot-Socketing Support | Yes | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | β |
| RoHS Status | Compliant (per -NAB suffix convention) | [DATA_NEEDED: RoHS compliance] |
| Delivery Form | Tray ('AB' suffix per Altera order code convention) | β |
| Process Technology | CMOS, EEPROM-based | β |
| Family | β | MAX 3000A |
| Macrocells | β | 32 |
| Logic Array Blocks (LABs) | β | 2 |
| User I/O Pins | β | 34 |
| Speed Grade | β | -4 (tPD = 4.5 ns) |
| Supply Voltage (Core) | β | 3.3 V |
| MultiVolt I/O Support | β | 1.8 V / 2.5 V / 3.3 V |
| In-System Programmability | β | IEEE 1149.1 (JTAG) |
| Technology | β | CMOS EEPROM |
| Erase/Program Cycles | β | 1000 |
| Data Retention | β | 20 years (minimum) |
| Open-Drain Output Option | β | Yes (per I/O pin) |