EPM3032ATC44-10NAB vs EPM3032ATC44-4 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3032ATC44-10NAB sa pamamagitan ng Intel at EPM3032ATC44-4 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM3032ATC44-10NAB - 32-Macrocell CPLD, 10ns, 3.3V | Intel (Altera)
EPM3032ATC44-10NAB ObsoleteIntel
EPM3032ATC44-4 - MAX 3000A CPLD, 32 Macrocells, 44-TQFP | Intel
EPM3032ATC44-4 ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EPM3032ATC44-10NAB | EPM3032ATC44-4 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Product Family | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Elements / Macrocells | 32 macrocells | — |
| Usable Gates | 600 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Operating Frequency | 103.1 MHz (per Arrow listing) | — |
| Number of User I/O | 34 (max for 44-pin TQFP package) | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V (MultiVolt I/O compatible with 5.0 V, 3.3 V, 2.5 V logic) | — |
| Packhaging | 44-pin TQFP | 44-pin TQFP |
| Uri ng Pagpapasok | Surface Mount | — |
| Programming Interface | JTAG (IEEE Std. 1149.1 / IEEE Std. 1532 ISP) | — |
| Configuration Memory | Non-volatile EEPROM | Non-volatile EEPROM |
| Hot-Socketing Support | Yes | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | — |
| Tindminan RoHS | Compliant (per -NAB suffix convention) | [DATA_NEEDED: RoHS compliance] |
| Delivery Form | Tray ('AB' suffix per Altera order code convention) | — |
| Process Technology | CMOS, EEPROM-based | — |
| Family | — | MAX 3000A |
| Macrocells | — | 32 |
| Logic Array Blocks (LABs) | — | 2 |
| User I/O Pins | — | 34 |
| Speed Grade | — | -4 (tPD = 4.5 ns) |
| Supply Voltage (Core) | — | 3.3 V |
| MultiVolt I/O Support | — | 1.8 V / 2.5 V / 3.3 V |
| In-System Programmability | — | IEEE 1149.1 (JTAG) |
| Technology | — | CMOS EEPROM |
| Erase/Program Cycles | — | 1000 |
| Data Retention | — | 20 years (minimum) |
| Open-Drain Output Option | — | Yes (per I/O pin) |