EPM3064ALC44-10N vs EPM3064ALC44-10 Comparison

Detailed side-by-side comparison of EPM3064ALC44-10N by Altera and EPM3064ALC44-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3064ALC44-10N EPM3064ALC44-10
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Product Family MAX 3000A —
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 64 —
Logic Array Blocks (LABs) 4 —
User I/O Pins 34 —
Usable Gates 1,250 1,250
Propagation Delay (tPD) 10 ns —
Maximum Counter Frequency 227.3 MHz —
Supply Voltage (VCCINT) 3.0 V to 3.6 V 3.3 V
I/O Bank Voltage (VCCIO) 3.0 V to 3.6 V (MultiVolt) —
Configuration Memory CMOS EEPROM —
In-System Programmability Yes (IEEE 1149.1 JTAG, IEEE 1532 compliant) —
Package 44-pin PLCC (LC44) 44-PLCC (J-Lead)
Mounting Type Surface Mount (PLCC socket compatible) Surface Mount (PLCC socket compatible)
Operating Temperature [DATA_NEEDED: commercial / industrial grade] 0°C to +70°C (commercial)
RoHS Status Compliant Compliant (lead-free L suffix indicates Pb-free package)
Open-Drain Output Option Yes (per I/O pin) —
Output Slew-Rate Control Programmable —
Family — MAX 3000A
Logic Elements / Macrocells — 64 macrocells
Number of Logic Array Blocks (LABs) — 4
Maximum User I/O Pins — 34
Pin-to-Pin Delay (tPD) — 10 ns
Maximum Counter Frequency (fCNT) — 192.3 MHz
Maximum Operating Frequency (fMAX) — [DATA_NEEDED: fMAX internal]
Process Technology — 0.30 µm CMOS EEPROM
Programmability — In-system programmable (JTAG IEEE 1149.1)
MultiVolt I/O — 2.5V / 3.3V / 5.0V interface compatible

Datasheets & Resources

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