EPM3064ATC-100-10N vs EPM3064ATC100-10N Comparison
Detailed side-by-side comparison of EPM3064ATC-100-10N by Altera and EPM3064ATC100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3064ATC100-10N - MAX 3000A CPLD, 64 Macrocells, 66 I/O | Altera
EPM3064ATC100-10N ✓ ActiveSpecification Comparison
| Parameter | EPM3064ATC-100-10N | EPM3064ATC100-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 64 | — |
| Logic Array Blocks (LABs) | 2 | 2 |
| User I/O Pins | 66 | — |
| Usable Gates (min) | 600 | — |
| Usable Gates (typical) | 1,250 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | 10 ns |
| Counter Frequency (fCNT) | 227.3 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V (3.0 V to 3.6 V) |
| In-System Programmability | Yes (IEEE 1532 / JTAG 1149.1) | Yes - IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| Programming Interface | 4-pin JTAG (TCK/TMS/TDI/TDO) | — |
| Package | TQFP-100 | 100-pin TQFP |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| RoHS Status | Compliant | Compliant (lead-free) |
| Macrocells | — | 64 |
| Maximum User I/O Pins | — | 66 |
| Usable Gates | — | 1,250 |
| Boundary-Scan Test (BST) | — | Yes - JTAG compliant |
| Configuration Memory | — | Non-volatile EEPROM |
| Program/Erase Cycles | — | 100 minimum |
| MultiVolt I/O | — | Yes - 1.8 V / 2.5 V / 3.3 V / 5 V tolerant |