EPM3064ATC44-10 vs EPM3064ATI44-10N Comparison
Detailed side-by-side comparison of EPM3064ATC44-10 by Altera and EPM3064ATI44-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3064ATC44-10
EPM3064ATC44-10 - 64-Macrocell MAX 3000A CPLD, TQFP-44 | Altera
EPM3064ATC44-10 ObsoleteAltera
EPM3064ATI44-10N
EPM3064ATI44-10N - 64-Macrocell 3.3V ISP CPLD | Intel / Altera
EPM3064ATI44-10N ObsoleteSpecification Comparison
| Parameter | EPM3064ATC44-10 | EPM3064ATI44-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $4.35 | $3.95 |
| Family | MAX 3000A | MAX 3000A |
| Logic Elements / Macrocells | 64 macrocells | β |
| Usable Gates | 1,250 | 1250 |
| Number of Logic Blocks / LABs | 4 LABs | β |
| Propagation Delay (tPD) | 10 ns | β |
| Maximum Internal Frequency | 227.3 MHz (counter speed) | β |
| Programmable I/Os | 34 | β |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V typical) | β |
| I/O Bank Voltage (VCCIO) | MultiVolt 1.5 V / 1.8 V / 2.5 V / 3.3 V | β |
| Technology | CMOS EEPROM, 5 V tolerant I/O | β |
| In-System Programming | IEEE Std. 1532 (JTAG) | β |
| Boundary-Scan Support | IEEE 1149.1 (JTAG) | β |
| Package | TQFP-44, 10 x 10 mm, 0.8 mm pitch | 44-pin TQFP |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature Range | 0C to +70C (commercial) | β |
| RoHS Status | Non-compliant (legacy Altera, Pb-bearing) | Non-Compliant (per digchip datasheet excerpt) |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| Macrocells | β | 64 |
| User I/Os | β | 34 |
| Dedicated Inputs | β | 4 |
| Logic Blocks | β | 4 |
| Pin-to-Pin Delay | β | 10 ns (-10 speed grade) |
| Maximum Frequency (fMAX) | β | 100 MHz |
| Programmable Type | β | In-System Programmable (EEPROM) |
| ISP Interface | β | IEEE Std. 1149.1 (JTAG) |
| ISP Standard Compliance | β | IEEE Std. 1532 |
| Core Supply Voltage (VCCINT) | β | 3.3 V |
| I/O Supply Voltage (VCCIO) | β | 3.3 V or 2.5 V (MultiVolt) |
| Operating Temperature | β | -40C to +85C (Industrial, "N" suffix) |
| Process Technology | β | CMOS EEPROM |
| Boundary-Scan Test | β | Built-in (JTAG) |
| Lead-Free Status | β | Contains Lead (per digchip datasheet excerpt) |