EPM3064ATI100-10N vs EPM3064ATC100-10N Comparison

Detailed side-by-side comparison of EPM3064ATI100-10N by Altera and EPM3064ATC100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3064ATI100-10N EPM3064ATC100-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Active
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Programmable Type In-System Programmable (ISP) via IEEE 1149.1 JTAG —
Technology CMOS EEPROM —
Usable Gates 1,250 1,250
Macrocells 64 64
Logic Array Blocks (LABs) 4 2
User I/O 66 —
Supply Voltage (Core / I/O) 3.3 V —
Pin-to-Pin Delay (tPD) 10 ns (-10 speed grade) 10 ns
Maximum Internal Frequency 227.3 MHz (counter) —
Package 100-pin TQFP (industrial) 100-pin TQFP
Operating Temperature -40 C to +85 C (industrial) 0C to +70C (commercial)
JTAG (IEEE 1149.1) Yes —
PCI Compliance PCI Local Bus Specification Revision 2.2 (-4/-5/-6/-7/-10 speed grades) —
MultiVolt I/O Supports 2.5 V / 3.3 V / 5 V mixed-voltage interfacing Yes - 1.8 V / 2.5 V / 3.3 V / 5 V tolerant
Lead-Free Status Contains Lead —
RoHS Status RoHS Non-Compliant Compliant (lead-free)
Maximum User I/O Pins — 66
Supply Voltage (VCCINT) — 3.3 V (3.0 V to 3.6 V)
In-System Programmability — Yes - IEEE Std. 1149.1 JTAG, IEEE Std. 1532
Boundary-Scan Test (BST) — Yes - JTAG compliant
Configuration Memory — Non-volatile EEPROM
Program/Erase Cycles — 100 minimum
Mounting Type — Surface Mount

Datasheets & Resources

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