EPM3064ATI44-4N vs EPM3064ATC44-10N Comparison
Detailed side-by-side comparison of EPM3064ATI44-4N by Altera and EPM3064ATC44-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM3064ATI44-4N | EPM3064ATC44-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Active |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $4.25 | $5.10 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Logic Elements / Macrocells | 64 macrocells | β |
| Usable Gates | 1,250 gates | 1250 |
| Number of Logic Array Blocks (LABs) | 4 LABs (16 macrocells each) | β |
| Maximum Operating Frequency | 222.2 MHz | β |
| Pin-to-Pin Propagation Delay (tPD) | 4.5 ns (-4 speed grade) | β |
| Supply Voltage - Core (VCCINT) | 3.3 V | β |
| Supply Voltage - I/O (VCCIO) | 3.3 V or 2.5 V | β |
| User I/O Pins | 34 I/O | 34 |
| Package | 44-pin TQFP | TQFP-44 (10x10 mm) |
| Operating Temperature | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Programming Interface | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 ISP | β |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: rohs status] | Compliant |
| Macro Cells | β | 64 |
| Logic Array Blocks (LABs) | β | 4 |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Maximum Counter Frequency | β | 192.3 MHz |
| Supply Voltage (VCCINT) | β | 3.3 V |
| I/O Standard | β | MultiVolt (mixed 1.5 V / 1.8 V / 2.5 V / 3.3 V) |
| In-System Programming | β | IEEE Std. 1532 compliant |
| Boundary-Scan Test | β | IEEE Std. 1149.1 (JTAG) compliant |
| Pin-Locking | β | Yes (across design iterations) |