EPM3064ATI44-4N vs EPM3064ATC44-10N Vergleich
Detaillierter Direktvergleich von EPM3064ATI44-4N von Altera und EPM3064ATC44-10N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3064ATI44-4N | EPM3064ATC44-10N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Aktiv |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $4,25 | $5,10 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Logic Elements / Macrocells | 64 macrocells | — |
| Usable Gates | 1,250 gates | 1250 |
| Number of Logic Array Blocks (LABs) | 4 LABs (16 macrocells each) | — |
| Maximum Operating Frequency | 222.2 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 4.5 ns (-4 speed grade) | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| Supply Voltage - I/O (VCCIO) | 3.3 V or 2.5 V | — |
| User I/O Pins | 34 I/O | 34 |
| Gehäuse | 44-pin TQFP | TQFP-44 (10x10 mm) |
| Betriebstemperatur | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Programming Interface | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 ISP | — |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) |
| Montageart | Surface Mount | Surface Mount |
| RoHS-Status | [DATA_NEEDED: rohs status] | Compliant |
| Macro Cells | — | 64 |
| Logic Array Blocks (LABs) | — | 4 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 192.3 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Standard | — | MultiVolt (mixed 1.5 V / 1.8 V / 2.5 V / 3.3 V) |
| In-System Programming | — | IEEE Std. 1532 compliant |
| Boundary-Scan Test | — | IEEE Std. 1149.1 (JTAG) compliant |
| Pin-Locking | — | Yes (across design iterations) |