EPM3064ATI44-7 vs EPM3064ATC44-7N Comparison

Detailed side-by-side comparison of EPM3064ATI44-7 by Altera and EPM3064ATC44-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3064ATI44-7 EPM3064ATC44-7N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $4.40 $2.30
Family MAX 3000A MAX 3000A
Product Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 64 β€”
Usable Gates 1,250 1,250
User I/O 34 β€”
Logic Array Blocks (LABs) 4 (16 macrocells each) β€”
Propagation Delay (tPD) 7.5 ns β€”
Maximum Internal Frequency (fMAX) 135.1 MHz β€”
Supply Voltage (VCCINT) 3.0 V to 3.6 V β€”
Supply Voltage (VCCIO) 3.0 V to 3.6 V β€”
Process Technology 0.30 Β΅m CMOS EEPROM β€”
Operating Temperature -40 Β°C to +85 Β°C (Industrial, 'I' suffix) 0Β°C to +85Β°C (commercial)
Package 44-pin TQFP (TI44) 44-pin TQFP
Mounting Type Surface Mount Surface Mount
In-System Programmability Yes, IEEE Std. 1532 compliant β€”
JTAG Support Yes (IEEE 1149.1) β€”
PCI Compliance Yes, speed grades -4/-5/-6/-7/-10 meet PCI SIG Rev. 2.2 β€”
RoHS Status [DATA_NEEDED: RoHS status] Compliant
MSL Level [DATA_NEEDED: MSL level] β€”
Device Type β€” CPLD (Complex Programmable Logic Device)
Macro Cells β€” 64
Logic Array Blocks β€” 2
User I/O Pins β€” 34
Number of Pins β€” 44
Speed Grade β€” -7 (7.5 ns pin-to-pin delay)
Pin-to-Pin Delay (tPD) β€” 7.5 ns
Maximum Counter Frequency β€” 192.3 MHz (-7 grade)
Supply Voltage (VCC) β€” 3.3 V
MultiVolt I/O β€” 1.8 V / 2.5 V / 3.3 V
Programmability β€” EEPROM, in-system programmable (ISP)
JTAG Interface β€” IEEE Std. 1149.1 compliant
ISP Standard β€” IEEE Std. 1532 compliant
Boundary-Scan Test (BST) β€” Built-in, JTAG-driven

Datasheets & Resources

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