EPM3064ATI44-7 vs EPM3064ATC44-7N Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM3064ATI44-7 disebabkan oleh Altera dan EPM3064ATC44-7N disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM3064ATI44-7 EPM3064ATC44-7N
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 3000A MAX 3000A
Product Type CPLD (Complex Programmable Logic Device) —
Macrocells 64 —
Usable Gates 1,250 1,250
User I/O 34 —
Logic Array Blocks (LABs) 4 (16 macrocells each) —
Propagation Delay (tPD) 7.5 ns —
Maximum Internal Frequency (fMAX) 135.1 MHz —
Supply Voltage (VCCINT) 3.0 V to 3.6 V —
Supply Voltage (VCCIO) 3.0 V to 3.6 V —
Process Technology 0.30 µm CMOS EEPROM —
Suhu Operasi -40 °C to +85 °C (Industrial, 'I' suffix) 0°C to +85°C (commercial)
Kemasan 44-pin TQFP (TI44) 44-pin TQFP
Jenis Pemasangan Surface Mount Surface Mount
In-System Programmability Yes, IEEE Std. 1532 compliant —
JTAG Support Yes (IEEE 1149.1) —
PCI Compliance Yes, speed grades -4/-5/-6/-7/-10 meet PCI SIG Rev. 2.2 —
Status RoHS [DATA_NEEDED: RoHS status] Compliant
Aras MSL [DATA_NEEDED: MSL level] —
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 64
Logic Array Blocks — 2
User I/O Pins — 34
Bilangan Pin — 44
Speed Grade — -7 (7.5 ns pin-to-pin delay)
Pin-to-Pin Delay (tPD) — 7.5 ns
Maximum Counter Frequency — 192.3 MHz (-7 grade)
Supply Voltage (VCC) — 3.3 V
MultiVolt I/O — 1.8 V / 2.5 V / 3.3 V
Programmability — EEPROM, in-system programmable (ISP)
JTAG Interface — IEEE Std. 1149.1 compliant
ISP Standard — IEEE Std. 1532 compliant
Boundary-Scan Test (BST) — Built-in, JTAG-driven

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