EPM3128AFC256-7N vs EPM3256AFC256-7 Comparison
Detailed side-by-side comparison of EPM3128AFC256-7N by Altera and EPM3256AFC256-7 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM3128AFC256-7N | EPM3256AFC256-7 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Architecture | CMOS EEPROM-based MAX | — |
| Macro Cells | 128 | 256 |
| Usable Gates | 2,500 | 10,000 |
| User I/Os | 98 | 161 |
| Propagation Delay (tPD) | 7.5 ns | — |
| Internal fMAX | 192.3 MHz | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| Supply Voltage - I/O (VCCIO) | 3.3 V or 2.5 V | — |
| Logic Family | CMOS | — |
| Programmability | In-system (ISP), IEEE Std. 1532, JTAG (IEEE Std. 1149.1) | — |
| Package | 256-BGA (FineLine, FBGA) | FBGA-256 (FineLine BGA), 256 balls |
| Operating Temperature | 0 C to +70 C (commercial) | 0 °C to 70 °C (Commercial) |
| Mounting Type | Surface Mount | — |
| Logic Array Blocks (LABs) | — | 16 |
| Pin-to-Pin Logic Delay | — | 4.5 ns (max) |
| Counter Frequency | — | 227.3 MHz (max) |
| Propagation Delay (tpd) | — | 10 ns |
| Core Voltage | — | 3.3 V |
| I/O Compatibility | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O) |
| Process Technology | — | CMOS EEPROM, 0.30 µm |
| In-System Programmability | — | IEEE Std. 1532-compliant 3.3-V ISP |
| Boundary-Scan Test | — | JTAG (IEEE 1149.1) |
| Speed Grade | — | -7 |
| RoHS Status | — | [DATA_NEEDED: RoHS compliance status] |