EPM3128ATC100-10NS vs EPM3128AFI256-10N Comparison

Detailed side-by-side comparison of EPM3128ATC100-10NS by Intel and EPM3128AFI256-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3128ATC100-10NS EPM3128AFI256-10N
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Active
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macro Cells 128 128
User I/Os 80 98
Pin Count 100 256
Package TQFP-100 256-ball FineLine BGA (FBGA-256)
Pin-to-Pin Logic Delay (tPD) 10 ns —
Counter Frequency (fCNT) up to 227.3 MHz —
Supply Voltage - Core (VCCINT) 3.3 V —
Supply Voltage - I/O (VCCIO) 3.3 V or 2.5 V (5.0 V-tolerant inputs) —
Logic-Level Compatibility 5.0 V, 3.3 V, 2.5 V —
Programmability In-system (ISP), IEEE Std. 1532 —
Boundary Scan IEEE 1149.1 JTAG —
Configuration Memory EEPROM (non-volatile) EEPROM (non-volatile)
Operating Temperature [DATA_NEEDED: operating temperature range] -40C to +85C (industrial, per 'I' suffix)
Mounting Type Surface Mount —
RoHS Status [DATA_NEEDED: RoHS compliance status] Compliant
Lead-Free [DATA_NEEDED: lead-free status] —
Logic Density — 2.5K gates
Speed Grade — -10 (10 ns pin-to-pin)
Propagation Delay (tPD) — 10 ns
Counter Frequency (max) — 227.3 MHz
Logic Family — CMOS, EEPROM-based
Supply Voltage (Core) — 3.3 V
I/O Compatibility — 5.0 V, 3.3 V, 2.5 V (MultiVolt)
In-System Programmability — Yes (JTAG / IEEE 1149.1)
PCI Compliance — PCI Local Bus Spec Rev 2.2

Datasheets & Resources

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