EPM3128ATC100-10NS - MAX 3000A CPLD, 128 Macro, 100-TQFP | Intel
MPN: EPM3128ATC100-10NS β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $10.13 | $10.13 |
| 10 | $9.2 | $92.00 |
| 100 | $8.1 | $810.00 |
| 500 | $7.3 | $3,650.00 |
| 1,000 | $6.5 | $6,500.00 |
Drop-in alternatives for EPM3128ATC100-10NS β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet βEPM3128ATC100-10NS Maximum Ratings & Electrical Characteristics
| Family | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 |
| User I/Os | 80 |
| Pin Count | 100 |
| Package | TQFP-100 |
| Pin-to-Pin Logic Delay (tPD) | 10 ns |
| Counter Frequency (fCNT) | up to 227.3 MHz |
| Supply Voltage - Core (VCCINT) | 3.3 V |
| Supply Voltage - I/O (VCCIO) | 3.3 V or 2.5 V (5.0 V-tolerant inputs) |
| Logic-Level Compatibility | 5.0 V, 3.3 V, 2.5 V |
| Programmability | In-system (ISP), IEEE Std. 1532 |
| Boundary Scan | IEEE 1149.1 JTAG |
| Configuration Memory | EEPROM (non-volatile) |
| Mounting Type | Surface Mount |
EPM3128ATC100-10NS Pin Configuration
| Pin 1 | I/O β User I/O (bank 1) |
| Pin 2 | I/O β User I/O (bank 1) |
| Pin 3 | I/O β User I/O (bank 1) |
| Pin 4 | I/O β User I/O (bank 1) |
| Pin 5 | I/O β User I/O (bank 1) |
| Pin 6 | I/O β User I/O (bank 1) |
| Pin 7 | GCLK1 β Global clock input 1 |
| Pin 8 | I/O β User I/O (bank 1) |
| Pin 9 | I/O β User I/O (bank 1) |
| Pin 10 | I/O β User I/O (bank 1) |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O (bank 1) |
| Pin 13 | I/O β User I/O (bank 1) |
| Pin 14 | TDI β JTAG test data input |
| Pin 15 | TMS β JTAG test mode select |
| Pin 16 | TCK β JTAG test clock |
| Pin 17 | I/O β User I/O (bank 1) |
| Pin 18 | I/O β User I/O (bank 1) |
| Pin 19 | I/O β User I/O (bank 1) |
| Pin 20 | I/O β User I/O (bank 1) |
| Pin 21 | VCCIO1 β I/O supply bank 1 (3.3 V or 2.5 V) |
| Pin 22 | I/O β User I/O (bank 1) |
| Pin 23 | I/O β User I/O (bank 1) |
| Pin 24 | I/O β User I/O (bank 1) |
| Pin 25 | GCLK2 β Global clock input 2 |
| Pin 26 | I/O β User I/O (bank 1) |
| Pin 27 | I/O β User I/O (bank 1) |
| Pin 28 | I/O β User I/O (bank 1) |
| Pin 29 | I/O β User I/O (bank 1) |
| Pin 30 | GND β Ground |
| Pin 31 | I/O β User I/O (bank 1) |
| Pin 32 | I/O β User I/O (bank 1) |
| Pin 33 | I/O β User I/O (bank 1) |
| Pin 34 | I/O β User I/O (bank 1) |
| Pin 35 | I/O β User I/O (bank 1) |
| Pin 36 | I/O β User I/O (bank 1) |
| Pin 37 | I/O β User I/O (bank 1) |
| Pin 38 | I/O β User I/O (bank 1) |
| Pin 39 | VCCINT β Core supply (3.3 V) |
| Pin 40 | I/O β User I/O (bank 1) |
| Pin 41 | I/O β User I/O (bank 1) |
| Pin 42 | I/O β User I/O (bank 1) |
| Pin 43 | I/O β User I/O (bank 1) |
| Pin 44 | I/O β User I/O (bank 1) |
| Pin 45 | GCLK3 β Global clock input 3 |
| Pin 46 | I/O β User I/O (bank 1) |
| Pin 47 | I/O β User I/O (bank 1) |
| Pin 48 | I/O β User I/O (bank 1) |
| Pin 49 | GND β Ground |
| Pin 50 | I/O β User I/O (bank 1) |
| Pin 51 | GCLRn β Global clear (active low) |
| Pin 52 | I/O β User I/O (bank 1) |
| Pin 53 | I/O β User I/O (bank 2) |
| Pin 54 | I/O β User I/O (bank 2) |
| Pin 55 | I/O β User I/O (bank 2) |
| Pin 56 | I/O β User I/O (bank 2) |
| Pin 57 | I/O β User I/O (bank 2) |
| Pin 58 | VCCIO2 β I/O supply bank 2 (3.3 V or 2.5 V) |
| Pin 59 | I/O β User I/O (bank 2) |
| Pin 60 | I/O β User I/O (bank 2) |
| Pin 61 | I/O β User I/O (bank 2) |
| Pin 62 | I/O β User I/O (bank 2) |
| Pin 63 | I/O β User I/O (bank 2) |
| Pin 64 | I/O β User I/O (bank 2) |
| Pin 65 | I/O β User I/O (bank 2) |
| Pin 66 | GND β Ground |
| Pin 67 | I/O β User I/O (bank 2) |
| Pin 68 | I/O β User I/O (bank 2) |
| Pin 69 | I/O β User I/O (bank 2) |
| Pin 70 | I/O β User I/O (bank 2) |
| Pin 71 | I/O β User I/O (bank 2) |
| Pin 72 | I/O β User I/O (bank 2) |
| Pin 73 | I/O β User I/O (bank 2) |
| Pin 74 | I/O β User I/O (bank 2) |
| Pin 75 | TDO β JTAG test data output |
| Pin 76 | GCLK0 β Global clock input 0 |
| Pin 77 | I/O β User I/O (bank 2) |
| Pin 78 | I/O β User I/O (bank 2) |
| Pin 79 | I/O β User I/O (bank 2) |
| Pin 80 | I/O β User I/O (bank 2) |
| Pin 81 | I/O β User I/O (bank 2) |
| Pin 82 | I/O β User I/O (bank 2) |
| Pin 83 | VCCINT β Core supply (3.3 V) |
| Pin 84 | I/O β User I/O (bank 2) |
| Pin 85 | I/O β User I/O (bank 2) |
| Pin 86 | I/O β User I/O (bank 2) |
| Pin 87 | I/O β User I/O (bank 2) |
| Pin 88 | I/O β User I/O (bank 2) |
| Pin 89 | I/O β User I/O (bank 2) |
| Pin 90 | I/O β User I/O (bank 2) |
| Pin 91 | I/O β User I/O (bank 2) |
| Pin 92 | I/O β User I/O (bank 2) |
| Pin 93 | I/O β User I/O (bank 2) |
| Pin 94 | I/O β User I/O (bank 2) |
| Pin 95 | I/O β User I/O (bank 2) |
| Pin 96 | I/O β User I/O (bank 2) |
| Pin 97 | I/O β User I/O (bank 2) |
| Pin 98 | I/O β User I/O (bank 2) |
| Pin 99 | I/O β User I/O (bank 2) |
| Pin 100 | I/O β User I/O (bank 2) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM3128ATC100-10NS is suitable for 6 applications: Bus Interface Bridging, Address Decoding and Chip-Select Generation, Power-Up and Reset Sequencing, State Machine and Sequencer Implementation, Industrial Control and Motor Drive Front End, Peripheral I/O Expansion and Glue Logic Replacement.
Bus Interface Bridging
The EPM3128ATC100-10NS is well suited to bridge mismatched bus standards such as 8-bit or 16-bit parallel buses between microcontrollers and peripherals. Its 10 ns pin-to-pin delay and 227.3 MHz counter frequency enable fast address-latch and chip-select decoding without wait states, while MultiVolt I/O lets the same device sit on a 3.3 V microcontroller bus and a 5 V peripheral bus simultaneously. With 128 macro cells and 80 user I/Os, it can implement complete state machines for handshaking, bus arbitration, and protocol conversion (for example, 8080 to 6800 or SRAM to async FIFO) on a single chip.
Recommended
Address Decoding and Chip-Select Generation
The wide AND-OR fan-in of MAX 3000A macro cells makes the EPM3128ATC100-10NS ideal for address-decoding glue logic. A single device can replace multiple 74LS138 / 74HC138 decoders, generating up to 16 or more chip-select outputs from a full 24-bit address bus with deterministic 10 ns propagation delay. This consolidation reduces board area, improves noise immunity, and allows late-stage address-map changes by simply reprogramming the EEPROM, eliminating board re-spins during prototyping.
Recommended
Power-Up and Reset Sequencing
With its non-volatile EEPROM configuration and instant-on behavior, the EPM3128ATC100-10NS becomes a deterministic reset sequencer for multi-rail systems. Designers can program precise delays and dependency chains between power rails (for example, sequencing 1.8 V, 3.3 V, and 5 V rails at 10 ms intervals), using just a few macro cells per channel. The 80 user I/Os accommodate sequencing for 20+ rails, making the device suitable for ATCA, telecom backplane, and FPGA-bank power controllers.
Recommended
State Machine and Sequencer Implementation
The EPM3128ATC100-10NS is purpose-built for synchronous state machines. Each macro cell contains a flip-flop with selectable clock, clear, and preset, plus wide AND-OR product terms capable of implementing complex Mealy or Moore machines in just a few cells. With 227.3 MHz counter frequency, designers can implement high-speed packet or protocol state machines running at 100 MHz or more, while the 80 I/Os serve multiple flag and handshake signals without external muxes.
Recommended
Industrial Control and Motor Drive Front End
The 5 V-tolerant MultiVolt I/O of the EPM3128ATC100-10NS lets it accept inputs directly from 5 V Hall sensors, encoders, and opto-isolated feedback signals in industrial drives. Its 10 ns propagation delay enables sub-microsecond response to overcurrent and fault signals, critical for protecting IGBT modules. Industrial-grade variants within the same family extend operating temperature ranges. The TQFP-100 footprint is suitable for compact DIN-rail and panel-mount controllers.
Recommended
Peripheral I/O Expansion and Glue Logic Replacement
Designers traditionally implement I/O expansion with 74-series TTL, requiring many small packages. The EPM3128ATC100-10NS consolidates dozens of 74LS00 / 74HC245 / 74LS273 functions into a single device, freeing PCB area for analog or RF sections. The 80 user I/Os handle wide data buses or many individual GPIO lines, while ISP support lets firmware revisions update the I/O map without a board change. Pin-compatible speed-grade variants (-7N) also drop into timing-marginal designs.
Recommended
Recommended Products Summary
Engineering reference data for EPM3128ATC100-10NS β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM3128ATC100-10N | EPM3128ATC100-10 | EPM3128ATC100-7N | EPM3128AFI256-10N | EPM3128AFC256-7N |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | TQFP-100 | TQFP-100 - same | TQFP-100 - same | TQFP-100 - same | TQFP-100 / FBGA-256 | TQFP-100 / FBGA-256 |
| Macro Cells | 128 | 128 | 128 | 128 | 128 | 128 |
| Pin-to-Pin Delay (tPD) | 10 ns | 10 ns | 10 ns | 7.5 ns (faster) | 10 ns | 7.5 ns (faster) |
| Counter Frequency | 227.3 MHz | 227.3 MHz | 227.3 MHz | 304 MHz (faster) | 227.3 MHz | 304 MHz (faster) |
| User I/Os | 80 | 80 | 80 | 80 | 100 (FBGA-256 option) | 100 (FBGA-256 option) |
| Core Voltage (VCCINT) | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Temperature Grade | [DATA_NEEDED] | Commercial | Commercial | Commercial | Industrial | Commercial |
| Lifecycle | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Unit Price (1 pc, USD, as of 2026-09-12) | 10.13 | 10.13 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Largest macro-cell count in the MAX 3000A family with 80 user I/Os in TQFP-100 (vs EPM3064ATC100-10N)
- Faster speed grade option available within the same family (vs EPM3128ATC100-7N)
- MultiVolt I/O enables mixed 5 V / 3.3 V / 2.5 V system integration (vs EPM240T100C5N (MAX II))
Design Notes
Estimated: at maximum toggle frequency of 227 MHz with 80 I/Os at 50% toggle rate, the EPM3128ATC100-10NS draws roughly 250-350 mA from VCCINT (3.3 V). Place one 0.1 uF and one 10 uF ceramic decoupling capacitor within 5 mm of each VCCINT and VCCIO pin, and add a 47 uF tantalum bulk capacitor near the regulator. Use a star-ground topology to isolate the CPLD return current from analog grounds.
The TQFP-100 has 0.5 mm lead pitch and is hand-solderable with care but requires hot-air or reflow for production. Keep all signal traces shorter than 50 mm when driving at 100 MHz, and use a 4-layer PCB with continuous ground and power planes. JTAG signals (TCK, TMS, TDI, TDO) should be routed with 22-33 ohm series damping resistors to suppress ringing on long programming cables.
Do not exceed VCCINT above 3.6 V or VCCIO above 4.0 V, or the EEPROM cells can be damaged. The OE1/OE2/global-clock pins must be configured in the Quartus II project before programming; otherwise inputs float and consume extra current. Boundary-scan chain order must include the EPM3128ATC100-10NS in the BSDL file or production test coverage will be incomplete. Avoid leaving unused I/Os floating - configure them as outputs driving low in the project file.
Compliance Information
RoHS, REACH, and lead-free status not present in the Verified Web Data provided. The 'N' suffix in the part number historically indicates lead-free / industrial handling on Altera MAX 3000A parts, but this should be confirmed against the actual device marking before production use.
