EPM3128ATI10010N vs EPM3128ATC100-10N Comparison
Detailed side-by-side comparison of EPM3128ATI10010N by Altera and EPM3128ATC100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3128ATC100-10N - 128-Macrocell MAX 3000A CPLD, 10ns, TQFP-100 | Intel
EPM3128ATC100-10N NrndSpecification Comparison
| Parameter | EPM3128ATI10010N | EPM3128ATC100-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | NRND |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | — |
| Usable Gates | 2,500 | 2500 |
| User I/Os | 80 | — |
| Number of Pins | 100 | — |
| Package | 100-pin TQFP | 100-pin TQFP (14 x 14 x 1.0 mm) |
| Mounting Type | Surface Mount | Surface Mount |
| Propagation Delay (tPD) | 10 ns | 10 ns |
| Maximum Internal Frequency | 98 MHz | — |
| Core Supply Voltage | 3.0 V to 3.6 V | — |
| I/O Bank Voltage | 1.8 V / 2.5 V / 3.3 V | — |
| Operating Temperature | 0 C to +70 C (commercial) | 0 °C to +70 °C (commercial) |
| Process Technology | CMOS EEPROM | — |
| Programming Interface | JTAG (IEEE 1149.1) ISP | — |
| PCI Compliance | Yes (speed grades -5/-6/-7/-10) | — |
| RoHS Status | unknown | Compliant |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Number of I/O | — | 80 |
| Logic Elements / Blocks | — | 8 LABs (16 macrocells each) |
| Maximum Internal Frequency (fMAX) | — | 98 MHz |
| Supply Voltage VCCINT | — | 3.3 V |
| I/O Bank Voltage VCCIO | — | 3.3 V or 2.5 V (selectable) |
| Configuration Memory | — | CMOS EEPROM (non-volatile, instant-on) |
| In-System Programming | — | IEEE Std. 1532-compliant ISP via JTAG |
| Lead-Free | — | Yes |
| MSL Level | — | 3 (per JEDEC J-STD-020) |