EPM3512AFC256-10 vs EPM3256AFC256-10N Comparison
Detailed side-by-side comparison of EPM3512AFC256-10 by Altera and EPM3256AFC256-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM3512AFC256-10 | EPM3256AFC256-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.50 | $25.95 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 256 |
| Logic Array Blocks (LABs) | 16 | β |
| Usable Gates | 10,000 | 5,000 gates |
| Maximum I/O Pins | 208 | β |
| Pin-to-Pin Delay (tPD) | 10 ns | β |
| Maximum Counter Frequency | 87 MHz | 227.3 MHz |
| Supply Voltage (VCCINT) | 3.3 V | β |
| I/O Voltage Tolerance | 5-V tolerant | β |
| Programmable Technology | CMOS EEPROM | β |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532) | β |
| Package | 256-pin FBGA | 256-pin FineLine BGA |
| Operating Temperature Range | [DATA_NEEDED: industrial/commercial operating temperature range] | β |
| Pin Count | 256 | β |
| Mounting Type | Surface Mount | β |
| RoHS Status | unknown | β |
| Architecture | MAX (Multiple Array matriX) EEPROM-based | β |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Maximum User I/O | β | 161 |
| Pin-to-Pin Logic Delay | β | 10 ns |
| Core Voltage | β | 3.3 V |
| I/O Logic Level Compatibility | β | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| Programmability | β | EEPROM, in-system programmable (ISP) |
| JTAG Interface | β | IEEE 1532 / JTAG (TDI, TDO, TMS, TCK) |
| Logic Family | β | CMOS |
| PCI Compliance | β | PCI Local Bus Specification Rev 2.2 (at -10 grade) |
| Operating Temperature | β | 0 C to 70 C (commercial) |