EPM3512AFC256-10 vs EPM3256AFC256-10N Vergleich
Detaillierter Direktvergleich von EPM3512AFC256-10 von Altera und EPM3256AFC256-10N von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM3512AFC256-10 | EPM3256AFC256-10N |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | NRND | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $17,50 | $25,95 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 256 |
| Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | 10,000 | 5,000 gates |
| Maximum I/O Pins | 208 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 87 MHz | 227.3 MHz |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Voltage Tolerance | 5-V tolerant | — |
| Programmable Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532) | — |
| Gehäuse | 256-pin FBGA | 256-pin FineLine BGA |
| Betriebstemperaturbereich | [DATA_NEEDED: industrial/commercial operating temperature range] | — |
| Pin-Anzahl | 256 | — |
| Montageart | Surface Mount | — |
| RoHS-Status | unknown | — |
| Architecture | MAX (Multiple Array matriX) EEPROM-based | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Maximum User I/O | — | 161 |
| Pin-to-Pin Logic Delay | — | 10 ns |
| Core Voltage | — | 3.3 V |
| I/O Logic Level Compatibility | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| Programmability | — | EEPROM, in-system programmable (ISP) |
| JTAG Interface | — | IEEE 1532 / JTAG (TDI, TDO, TMS, TCK) |
| Logic Family | — | CMOS |
| PCI Compliance | — | PCI Local Bus Specification Rev 2.2 (at -10 grade) |
| Betriebstemperatur | — | 0 C to 70 C (commercial) |