EPM3512AFC256-21 vs EPM3512AFC256-10N Comparison

Detailed side-by-side comparison of EPM3512AFC256-21 by Altera and EPM3512AFC256-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AFC256-21 EPM3512AFC256-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status NRND Obsolete
Device Family MAX 3000A —
Logic Elements / Macrocells 512 macrocells —
Usable Gates 10,000 10000
Logic Array Blocks (LABs) 16 [DATA_NEEDED: number of LABs]
Maximum Operating Frequency 87 MHz —
Package FBGA-256 (FineLine BGA) 256-ball FBGA (17 mm x 17 mm)
Operating Temperature -40C to +85C (industrial) —
Supply Voltage - Core (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V (multi-volt I/O) —
Programmable Pins (max) [DATA_NEEDED: maximum user I/O pin count] —
Programming Interface JTAG / IEEE Std. 1532 ISP —
Memory Type Non-volatile EPROM/EEPROM cell array —
Mounting Type Surface Mount (BGA) Surface Mount (BGA)
RoHS Status [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Lead-Free [DATA_NEEDED: lead-free status] —
Family — MAX 3000A
Macrocells — 512
User I/O Pins — 208
Operating Frequency (fMAX) — [DATA_NEEDED: fMAX MHz]
Pin-to-Pin Delay (tPD) — 10 ns
Setup Time (tSU) — 4.5 ns
VCCINT (Core Supply) — 3.3 V
VCCIO (I/O Supply) — 3.3 V or 2.5 V
Technology — CMOS EEPROM-based, non-volatile
Operating Temperature (Commercial) — 0 C to +70 C
ISP Interface — IEEE Std. 1149.1 JTAG, IEEE Std. 1532
MSL Level — [DATA_NEEDED: MSL rating]

Datasheets & Resources

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