EPM3512AFC256-5C vs EPM3512AFC256-10 Comparison
Detailed side-by-side comparison of EPM3512AFC256-5C by Altera and EPM3512AFC256-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3512AFC256-5C - MAX 3000A CPLD, 512 Macrocells, 256-BGA | Altera
EPM3512AFC256-5C Obsolete
Specification Comparison
| Parameter | EPM3512AFC256-5C | EPM3512AFC256-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | 10,000 |
| Maximum Operating Frequency | 95.2 MHz | — |
| Pin-to-Pin Delay (tPD) | 5 ns | 10 ns |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| I/O Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (banked MultiVolt I/O) | — |
| User I/O Pins | 212 (max) | — |
| Package | 256-ball FBGA, 17 mm × 17 mm, 1.0 mm pitch | 256-pin FBGA |
| Operating Temperature | 0 °C to +70 °C (commercial, "C" grade) | — |
| Programming Interface | IEEE Std. 1532 / JTAG (4-wire) in-system programmable | — |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS status] | unknown |
| Technology | EEPROM-based macrocell, non-volatile | — |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum I/O Pins | — | 208 |
| Maximum Counter Frequency | — | 87 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage Tolerance | — | 5-V tolerant |
| Programmable Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532) |
| Operating Temperature Range | — | [DATA_NEEDED: industrial/commercial operating temperature range] |
| Pin Count | — | 256 |
| Architecture | — | MAX (Multiple Array matriX) EEPROM-based |