EPM3512AFC256-7N vs EPM3512AFC256-5C Comparison

Detailed side-by-side comparison of EPM3512AFC256-7N by Altera and EPM3512AFC256-5C by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AFC256-7N EPM3512AFC256-5C
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Family MAX 3000A MAX 3000A
Product Type CPLD (Complex Programmable Logic Device) —
Macrocells 512 512
Usable Gates 10,000 10,000
User I/Os 208 —
Logic Blocks 16 (32 macrocells each) —
Propagation Delay (tPD) 7.5 ns —
Maximum Internal Frequency (fMAX) 116.3 MHz —
Core Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 3.3 V or 2.5 V —
5V Tolerant I/O Yes —
In-System Programmability IEEE Std. 1532 compliant —
Programming Interface JTAG (IEEE 1149.1) IEEE Std. 1532 / JTAG (4-wire) in-system programmable
Process Technology CMOS EEPROM, 0.30 um —
Package 256-pin FineLine BGA (FBGA-256), 1.0 mm pitch 256-ball FBGA, 17 mm × 17 mm, 1.0 mm pitch
Operating Temperature 0 C to 70 C (commercial) 0 °C to +70 °C (commercial, "C" grade)
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Device Type — CPLD (Complex Programmable Logic Device)
Maximum Operating Frequency — 95.2 MHz
Pin-to-Pin Delay (tPD) — 5 ns
Supply Voltage - Core (VCCINT) — 3.3 V
I/O Voltage (VCCIO) — 2.5 V / 3.3 V / 5.0 V (banked MultiVolt I/O)
User I/O Pins — 212 (max)
Technology — EEPROM-based macrocell, non-volatile

Datasheets & Resources

Browse All Products Create BOM Request Quote