EPM3512AFC256-7N vs EPM3512AFC256-5C 비교
다음의 상세 나란히 비교: EPM3512AFC256-7N 제조: Altera 및 EPM3512AFC256-5C 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Altera
EPM3512AFC256-7N - MAX 3000A CPLD, 512 Macrocells, 208 I/O | Altera
EPM3512AFC256-7N ObsoleteAltera
EPM3512AFC256-5C - MAX 3000A CPLD, 512 Macrocells, 256-BGA | Altera
EPM3512AFC256-5C Obsolete사양 비교
| 파라미터 | EPM3512AFC256-7N | EPM3512AFC256-5C |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $61.00 | $28.95 |
| Family | MAX 3000A | MAX 3000A |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | 10,000 |
| User I/Os | 208 | — |
| Logic Blocks | 16 (32 macrocells each) | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Internal Frequency (fMAX) | 116.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 2.5 V | — |
| 5V Tolerant I/O | Yes | — |
| In-System Programmability | IEEE Std. 1532 compliant | — |
| Programming Interface | JTAG (IEEE 1149.1) | IEEE Std. 1532 / JTAG (4-wire) in-system programmable |
| Process Technology | CMOS EEPROM, 0.30 um | — |
| 패키지 | 256-pin FineLine BGA (FBGA-256), 1.0 mm pitch | 256-ball FBGA, 17 mm × 17 mm, 1.0 mm pitch |
| 동작 온도 | 0 C to 70 C (commercial) | 0 °C to +70 °C (commercial, "C" grade) |
| 실장 유형 | Surface Mount | Surface Mount |
| RoHS 상태 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Maximum Operating Frequency | — | 95.2 MHz |
| Pin-to-Pin Delay (tPD) | — | 5 ns |
| Supply Voltage - Core (VCCINT) | — | 3.3 V |
| I/O Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (banked MultiVolt I/O) |
| User I/O Pins | — | 212 (max) |
| Technology | — | EEPROM-based macrocell, non-volatile |