EPM3512AFI256-10 vs EPM3512AFC256-5C Comparison

Detailed side-by-side comparison of EPM3512AFI256-10 by Intel and EPM3512AFC256-5C by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AFI256-10 EPM3512AFC256-5C
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $18.75 $28.95
Family MAX 3000A MAX 3000A
Product Type CPLD (Complex Programmable Logic Device) β€”
Equivalent Gates 10,000 β€”
Macrocells 512 512
User I/Os 208 β€”
Pin-to-Pin Logic Delay (tPD) 4.5 ns β€”
Maximum Counter Frequency 227.3 MHz β€”
Propagation Delay 7.5 ns (max, per chipdig summary) β€”
Core Voltage 3.3 V β€”
MultiVolt I/O Levels 5.0 V / 3.3 V / 2.5 V β€”
Process Technology CMOS EEPROM β€”
In-System Programmability Yes, IEEE Std. 1532 (3.3 V ISP) β€”
Package FBGA-256 (FineLine BGA, 256 balls) 256-ball FBGA, 17 mm Γ— 17 mm, 1.0 mm pitch
Operating Temperature 0C to +70C (commercial) 0 Β°C to +70 Β°C (commercial, "C" grade)
Logic Family CMOS β€”
RoHS Status [DATA_NEEDED: rohs_status] [DATA_NEEDED: RoHS status]
Supply Voltage 3.3 V (core); MultiVolt I/O to 5.0 V β€”
Device Type β€” CPLD (Complex Programmable Logic Device)
Usable Gates β€” 10,000
Maximum Operating Frequency β€” 95.2 MHz
Pin-to-Pin Delay (tPD) β€” 5 ns
Supply Voltage - Core (VCCINT) β€” 3.3 V
I/O Voltage (VCCIO) β€” 2.5 V / 3.3 V / 5.0 V (banked MultiVolt I/O)
User I/O Pins β€” 212 (max)
Programming Interface β€” IEEE Std. 1532 / JTAG (4-wire) in-system programmable
Mounting Type β€” Surface Mount
Technology β€” EEPROM-based macrocell, non-volatile

Datasheets & Resources

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