EPM3512AFI256-10 vs EPM3512AFC256-5C 对比

详细并排对比 EPM3512AFI256-10 出自 Intel 和 EPM3512AFC256-5C 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3512AFI256-10 EPM3512AFC256-5C
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 有效 Obsolete
库存状态 有库存 有库存
单价(USD) $18.75 $28.95
Family MAX 3000A MAX 3000A
Product Type CPLD (Complex Programmable Logic Device) —
Equivalent Gates 10,000 —
Macrocells 512 512
User I/Os 208 —
Pin-to-Pin Logic Delay (tPD) 4.5 ns —
Maximum Counter Frequency 227.3 MHz —
Propagation Delay 7.5 ns (max, per chipdig summary) —
Core Voltage 3.3 V —
MultiVolt I/O Levels 5.0 V / 3.3 V / 2.5 V —
Process Technology CMOS EEPROM —
In-System Programmability Yes, IEEE Std. 1532 (3.3 V ISP) —
封装 FBGA-256 (FineLine BGA, 256 balls) 256-ball FBGA, 17 mm × 17 mm, 1.0 mm pitch
工作温度 0C to +70C (commercial) 0 °C to +70 °C (commercial, "C" grade)
Logic Family CMOS —
RoHS 状态 [DATA_NEEDED: rohs_status] [DATA_NEEDED: RoHS status]
电源电压 3.3 V (core); MultiVolt I/O to 5.0 V —
Device Type — CPLD (Complex Programmable Logic Device)
Usable Gates — 10,000
Maximum Operating Frequency — 95.2 MHz
Pin-to-Pin Delay (tPD) — 5 ns
Supply Voltage - Core (VCCINT) — 3.3 V
I/O Voltage (VCCIO) — 2.5 V / 3.3 V / 5.0 V (banked MultiVolt I/O)
User I/O Pins — 212 (max)
Programming Interface — IEEE Std. 1532 / JTAG (4-wire) in-system programmable
安装类型 — Surface Mount
Technology — EEPROM-based macrocell, non-volatile

数据手册与资源

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