EPM3512AFI256-10N vs EPM3512AQI208-10N Comparison
Detailed side-by-side comparison of EPM3512AFI256-10N by Altera and EPM3512AQI208-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3512AFI256-10N - 512-Macro MAX 3000A CPLD, 256-FBGA | Intel/Altera
EPM3512AFI256-10N ⚠ Last Time Buy
Specification Comparison
| Parameter | EPM3512AFI256-10N | EPM3512AQI208-10N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last Time Buy | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Series | EPM3512 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | CMOS EEPROM-based, MAX architecture | — |
| Number of Macrocells | 512 | — |
| Number of Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | Up to 10,000 | — |
| Number of User I/O | 208 | — |
| Total Pins | 256 | — |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 227.3 MHz | — |
| Core Supply Voltage (VCCINT) | 3.3 V (3.0 V to 3.6 V) | — |
| I/O Supply Voltage (VCCIO) | 2.5 V or 3.3 V (5.0 V tolerant inputs) | — |
| MultiVolt I/O Support | 5.0 V / 3.3 V / 2.5 V | — |
| In-System Programmability | Yes - IEEE Std 1532 compliant | — |
| JTAG Boundary Scan | Yes - IEEE 1149.1 | — |
| Program Memory | EEPROM (non-volatile) | — |
| Package | 256-ball FineLine BGA (FBGA-256) | — |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature Range | -40 °C to +85 °C (industrial) | — |
| RoHS Status | Compliant | — |
| Speed Grade | -10 (10 ns tPD) | — |
| Logic Family | — | CMOS EEPROM-based |
| Macro Cells | — | 512 |
| Logic Array Blocks (LABs) | — | 12 |
| User I/Os | — | 172 (max), 208-pin package |
| Propagation Delay (tPD) | — | 10 ns |
| Supply Voltage | — | 3.3 V |
| I/O Standards | — | MultiVolt (2.5 V / 3.3 V / 5 V tolerant) |
| Package Type | — | PQFP-208 (FINE LINE BGA-style 256-pin land) |
| Pins | — | 256 (package), 208 used |
| Operating Temperature | — | 0C to 70C |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP (IEEE 1532) |
| Compliance | — | RoHS status unknown from data |
| Boundary Scan | — | Built-in BST (IEEE 1149.1) |
| Configuration Memory | — | On-chip EEPROM, non-volatile |