EPM3512AQC20-10 vs EPM3512AFC256-7 Comparison

Detailed side-by-side comparison of EPM3512AQC20-10 by Altera and EPM3512AFC256-7 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC20-10 EPM3512AFC256-7
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Last_time_buy
Stock Status In Stock In Stock
Unit Price (USD) $21.10 $58.40
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 512 512
Logic Array Blocks (LABs) 16 16
Macrocells per LAB 32 β€”
User I/O Pins 100 212
Pin-to-Pin Delay (tPD) 10 ns β€”
Maximum Frequency (fCNT) 116.3 MHz β€”
Supply Voltage VCCINT 5.0 V β€”
MultiVolt I/O Voltages 5.0 V / 3.3 V / 2.5 V / 1.8 V β€”
Programming Interface IEEE 1149.1 (JTAG) - In-System Programmable β€”
Process Technology 0.30 Β΅m EEPROM CMOS β€”
Package PQFP-240 (QC20 designation per Altera ordering code) 256-ball FineLine BGA (FBGA-256)
Operating Temperature 0C to +70C (commercial) [DATA_NEEDED: operating temperature grade]
RoHS Status Compliant (lead-free PQFP package) [DATA_NEEDED: RoHS status]
Usable Gates β€” 10,000
Pin-to-Pin Logic Delay β€” 7.5 ns
Counter Frequency (max) β€” 227.3 MHz
Supply Voltage - Core (VCCINT) β€” 3.0 V to 3.6 V (3.3 V typ.)
I/O Voltage (VCCIO) β€” 5.0 V / 3.3 V / 2.5 V (MultiVolt)
Programming β€” EEPROM, IEEE 1149.1 JTAG ISP (IEEE 1532-compliant)
Mounting Type β€” Surface Mount
Configuration Memory β€” Non-volatile EEPROM

Datasheets & Resources

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