EPM3512AQC20-10 vs EPM3512AQC208-10N Comparison
Detailed side-by-side comparison of EPM3512AQC20-10 by Altera and EPM3512AQC208-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM3512AQC20-10 | EPM3512AQC208-10N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Macrocells per LAB | 32 | — |
| User I/O Pins | 100 | — |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Frequency (fCNT) | 116.3 MHz | — |
| Supply Voltage VCCINT | 5.0 V | — |
| MultiVolt I/O Voltages | 5.0 V / 3.3 V / 2.5 V / 1.8 V | — |
| Programming Interface | IEEE 1149.1 (JTAG) - In-System Programmable | — |
| Process Technology | 0.30 µm EEPROM CMOS | CMOS EEPROM |
| Package | PQFP-240 (QC20 designation per Altera ordering code) | 208-pin PQFP (Plastic Quad Flat Pack) |
| Operating Temperature | 0C to +70C (commercial) | 0 C to 70 C (commercial) |
| RoHS Status | Compliant (lead-free PQFP package) | [DATA_NEEDED: RoHS status not in verified web data] |
| Usable Gates | — | Up to 10,000 |
| User I/Os | — | 172 |
| Supply Voltage | — | 3.3 V |
| Pin-to-Pin Delay | — | 4.5 ns (-10 speed grade) |
| Maximum Internal Frequency | — | 227.3 MHz |
| Speed Grade | — | -10 |
| In-System Programming | — | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | Built-in, IEEE 1149.1 compliant |
| I/O Standards | — | MultiVolt (1.8V / 2.5V / 3.3V) |