EPM3512AQC208-10-10N vs EPM3512AQC208-10NS Comparison

Detailed side-by-side comparison of EPM3512AQC208-10-10N by Altera and EPM3512AQC208-10NS by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC208-10-10N EPM3512AQC208-10NS
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Active
Family MAX 3000A MAX 3000A
Macrocells 512 —
Usable Gates 10,000 10,000
User I/Os 172 172
Logic Elements / LABs 16 Logic Array Blocks —
Propagation Delay (tPD) 10 ns (-10 speed grade) —
Maximum Frequency (fCNT) 87 MHz —
Supply Voltage - Core (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V 2.5 V / 3.3 V / 5.0 V (MultiVolt)
Process Technology CMOS EEPROM —
In-System Programmability Yes, IEEE Std. 1532 compliant —
Boundary-Scan (JTAG) Yes, IEEE 1149.1 —
PCI-SIG Compliance PCI Local Bus Specification Rev 2.2 (at -10 speed grade) —
Operating Temperature 0 °C to +70 °C (commercial) 0C to +70C (commercial)
Package 208-pin PQFP (Plastic Quad Flat Pack) 208-pin PQFP
Mounting Type Surface Mount Surface Mount
Lead-Free / RoHS [DATA_NEEDED: RoHS status] —
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 512
Logic Array Blocks (LABs) — 12
Pin-to-Pin Delay (tPD) — 10 ns (speed grade -10)
Internal Counter Frequency — 227.3 MHz max
Propagation Delay — 7.5 ns (datasheet figure)
Core Supply Voltage (VCCINT) — 3.3 V
Logic Family — CMOS, EEPROM-based
Configuration — Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532)
ISP Standard — IEEE Std. 1532
RoHS Status — [DATA_NEEDED: rohs status]

Datasheets & Resources

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