EPM3512AQC208-10-10N vs EPM3512AQC208-10NS 对比
详细并排对比 EPM3512AQC208-10-10N 出自 Altera 和 EPM3512AQC208-10NS 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
Altera
EPM3512AQC208-10-10N - MAX 3000A CPLD 512 Macrocells 208-PQFP | Altera
EPM3512AQC208-10-10N Obsolete规格对比
| 参数 | EPM3512AQC208-10-10N | EPM3512AQC208-10NS |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | 有效 |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $31.20 | $32.40 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | — |
| Usable Gates | 10,000 | 10,000 |
| User I/Os | 172 | 172 |
| Logic Elements / LABs | 16 Logic Array Blocks | — |
| Propagation Delay (tPD) | 10 ns (-10 speed grade) | — |
| Maximum Frequency (fCNT) | 87 MHz | — |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| Process Technology | CMOS EEPROM | — |
| In-System Programmability | Yes, IEEE Std. 1532 compliant | — |
| Boundary-Scan (JTAG) | Yes, IEEE 1149.1 | — |
| PCI-SIG Compliance | PCI Local Bus Specification Rev 2.2 (at -10 speed grade) | — |
| 工作温度 | 0 °C to +70 °C (commercial) | 0C to +70C (commercial) |
| 封装 | 208-pin PQFP (Plastic Quad Flat Pack) | 208-pin PQFP |
| 安装类型 | Surface Mount | Surface Mount |
| Lead-Free / RoHS | [DATA_NEEDED: RoHS status] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 512 |
| Logic Array Blocks (LABs) | — | 12 |
| Pin-to-Pin Delay (tPD) | — | 10 ns (speed grade -10) |
| Internal Counter Frequency | — | 227.3 MHz max |
| Propagation Delay | — | 7.5 ns (datasheet figure) |
| Core Supply Voltage (VCCINT) | — | 3.3 V |
| Logic Family | — | CMOS, EEPROM-based |
| Configuration | — | Non-volatile EEPROM, in-system programmable (JTAG IEEE 1532) |
| ISP Standard | — | IEEE Std. 1532 |
| RoHS 状态 | — | [DATA_NEEDED: rohs status] |