EPM3512AQC208-10N vs EPM3512AQC208-3N Comparison

Detailed side-by-side comparison of EPM3512AQC208-10N by Intel and EPM3512AQC208-3N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC208-10N EPM3512AQC208-3N
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $42.80 $16.40
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 512 512
Usable Gates Up to 10,000 β€”
Logic Array Blocks (LABs) 16 16
User I/Os 172 β€”
Package 208-pin PQFP (Plastic Quad Flat Pack) PQFP-208
Supply Voltage 3.3 V β€”
Pin-to-Pin Delay 4.5 ns (-10 speed grade) β€”
Maximum Internal Frequency 227.3 MHz β€”
Speed Grade -10 β€”
Process Technology CMOS EEPROM β€”
In-System Programming IEEE Std. 1149.1 JTAG, IEEE Std. 1532 β€”
Boundary-Scan Test (BST) Built-in, IEEE 1149.1 compliant β€”
I/O Standards MultiVolt (1.8V / 2.5V / 3.3V) β€”
Operating Temperature 0 C to 70 C (commercial) 0C to +70C (commercial)
RoHS Status [DATA_NEEDED: RoHS status not in verified web data] [DATA_NEEDED: not stated in retrieved snippets]
User I/O Pins β€” 172
Macrocells per LAB β€” 32
Pin-to-Pin Logic Delay β€” 3 ns (speed grade -3)
Global Clock Setup Time β€” [DATA_NEEDED: actual tSU at 3 ns grade]
Core Supply Voltage (VCCINT) β€” 3.3 V
I/O Supply Voltage (VCCIO) β€” 3.3 V (MultiVolt 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant)
Mounting Type β€” Surface Mount
Programming Technology β€” EEPROM (non-volatile, in-system programmable)
JTAG / Boundary Scan β€” IEEE 1149.1 compliant
ISP Compliance β€” IEEE Std. 1532
Lead-Free / Halogen-Free β€” [DATA_NEEDED]

Datasheets & Resources

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